This chapter contains information about the example designs provided in the AMD Vivado™ Design Suite.
Tip: The
PCIe reset pin for PL PCIE designs can be connected to any compatible single ended
PL I/O pin location. If your board is compatible for either CPM4 or PL PCIE usage,
you can use the CPM4 pin MIO38 to route the
sys_rst_n. When this is done, the PL PCIE can use the reset as routed
to the PL. Before opening the example design, set the following Tcl property to
use the reset on the MIO38
pin:
set_property CONFIG.insert_cips {true} [get_ips pcie_versal_0]