FLR Control/Status Register (0x22500) - 2.0 English

Versal Adaptive SoC DMA and Bridge Subsystem for PCI Express Product Guide (PG344)

Document ID
PG344
Release Date
2023-11-10
Version
2.0 English
Table 1. FLR Control/Status Register (0x22500)
Bit Default Access Type Field Description
[31:1] 0 NA Reserved Reserved
[0] 0 RW Flr_status Software write 1 to initiate the Function Level Reset (FLR) for the associated function. The field is kept asserted during the FLR process. After the FLR is done, the hardware de-asserts this field.