H2C Channel Performance Monitor Control (0xC0) - 2.0 English

Versal Adaptive SoC DMA and Bridge Subsystem for PCI Express Product Guide (PG344)

Document ID
PG344
Release Date
2023-11-10
Version
2.0 English
Table 1. H2C Channel Performance Monitor Control (0xC0)
Bit Index Default Access Type Description
2 1’b0 RW

Run

Set to 1 to arm performance counters. Counter starts after the Control register Run bit is set.

Set to 0 to halt performance counters.

1 1’b0 WO

Clear

Write 1 to clear performance counters.

0 1’b0 RW

Auto

Automatically stop performance counters when a descriptor with the stop bit is completed. Automatically clear performance counters when the Control register Run bit is set. Writing 1 to the Performance Monitor Control register Run bit is still required to start the counters.