H2C SGDMA Descriptor Low Address (0x80)

H2C SGDMA Descriptor Low Address (0x80) - 2.0 English

Versal Adaptive SoC DMA and Bridge Subsystem for PCI Express Product Guide (PG344)

Document ID

PG344

Release Date

2023-11-10

Version

2.0 English

Table 1. H2C SGDMA Descriptor Low Address (0x80)
Bit Index	Default	Access Type	Description
31:0	32’h0	RW	dsc_adr[31:0] Lower bits of start descriptor address. Dsc_adr[63:0] is the first descriptor address that is fetched after the Control register Run bit is set.