IRQ Block Registers (0x2) - 2.0 English

Versal Adaptive SoC DMA and Bridge Subsystem for PCI Express Product Guide (PG344)
Document ID
PG344
Release Date
2023-11-10
Version
2.0 English

The IRQ Block registers are described in this section.

Table 1. IRQ Block Register Space
Address (hex) Register Name
0x00 IRQ Block Identifier (0x00)
0x04 IRQ Block User Interrupt Enable Mask (0x04)
0x08 IRQ Block User Interrupt Enable Mask (0x08)
0x0C IRQ Block User Interrupt Enable Mask (0x0C)
0x10 IRQ Block Channel Interrupt Enable Mask (0x10)
0x14 IRQ Block Channel Interrupt Enable Mask (0x14)
0x18 IRQ Block Channel Interrupt Enable Mask (0x18)
0x40 IRQ Block User Interrupt Request (0x40)
0x44 IRQ Block Channel Interrupt Request (0x44)
0x48 IRQ Block User Interrupt Pending (0x48)
0x4C IRQ Block Channel Interrupt Pending (0x4C)
0x80 IRQ Block User Vector Number (0x80)
0x84 IRQ Block User Vector Number (0x84)
0x88 IRQ Block User Vector Number (0x88)
0x8C IRQ Block User Vector Number (0x8C)
0xA0 IRQ Block Channel Vector Number (0xA0)
0xA4 IRQ Block Channel Vector Number (0xA4)

Interrupt processing registers are shared between AXI Bridge and AXI DMA. In AXI Bridge mode when MSI-X Capabilities is selected, 64 KB address space from the BAR0 is reserved for the MSI-X table. By default, register space is allocated in BAR0. You can select register space in a different BAR, from BAR1 to BAR5, by using the CONFIG.bar_indicator {BAR0} Tcl command. This option is valid only when MSI-X Capabilities option is selected. There is no allocated space for other interrupt options.