The interface signals for the Bridge are described in the following table.
| Signal Name | I/O | Description |
|---|---|---|
| usr_irq_in_vld | I | Valid An assertion indicates that an interrupt associated with the vector, function, and pending fields on the bus should be generated to PCIe. Once asserted, Usr_irq_in_vld must remain high until usr_irq_out_ack is asserted by the DMA. |
| usr_irq_in_vec [10:0] | I | Vector The MSIX vector to be sent. |
| usr_irq_in_fnc [7:0] | I | Function The function of the vector to be sent. |
| usr_irq_out_ack | O | Interrupt Acknowledge An assertion of the acknowledge bit indicates that the interrupt was transmitted on the link the user logic must wait for this pulse before signaling another interrupt condition. |
| usr_irq_out_fail | O | Interrupt Fail An assertion of fail indicates that the interrupt request was aborted before transmission on the link. |