Legacy INTx Interrupt - 2.0 English

Versal Adaptive SoC DMA and Bridge Subsystem for PCI Express Product Guide (PG344)

Document ID
PG344
Release Date
2023-11-10
Version
2.0 English

When the IP has received an INTx interrupt, the Interrupt Decode 2 register is set. If the Interrupt Mask 2 register is also set, the interrupt_out pin is asserted. After receiving this interrupt, the user application must follow this procedure to service the interrupt:

  1. Optional: Write 0 to the Interrupt Mask 2 register to deassert an interrupt line while the interrupt is being serviced.
  2. Read the Interrupt Decode 2 register to check which interrupt line is currently asserted.
  3. Repeat step 2 until all interrupt lines are deasserted. The interrupt line is automatically cleared when the IP receives the INTx deassert message corresponding to that interrupt line.
  4. If step 1 was executed, write 1 to the Interrupt Mask 2 register to re-enable an interrupt line for future INTx interrupt.