Versal ACAP PHY for PCI Express LogiCORE IP Product Guide (PG345) - 1.0 English

Document ID: PG345
Release Date: 2022-11-04
Version: 1.0 English

Introduction
Features
Versal ACAP PHY for PCI Express Features
Versal Premium ACAP PHY for PCI Express Features
IP Facts
Overview
Navigating Content by Design Process
Core Overview
Feature Summary
Versal ACAP PHY for PCI Express Support
Versal Premium ACAP PHY for PCI Express Support
Unsupported Features
Versal ACAP PHY for PCI Express Unsupported Features
Versal Premium ACAP PHY for PCI Express Unsupported Features
Licensing and Ordering
Product Specification
Versal ACAP PHY for PCI Express
Versal Premium ACAP PHY for PCI Express
Performance and Resource Use
Minimum Device Requirements
Port Descriptions
Clock and Rest Signals Interface Ports
TX Data Signals
RX Data Signals
Command Signals Interface Ports
Status Signals Interface Ports
TX Driver Signal Interface Ports
TX Equalization Interface Ports for Third-Party MAC
Interface Ports RX Equalization Signals for Third-Party MAC
PIPE RX Margin (To GT Quad)
PIPE RX Margin (To MAC)
TX Equalization Signals for Gen3 and Gen4 (for Xilinx MAC)
Miscellaneous Ports for Xilinx PCIe MAC
Designing with the Core
Clocking
Resets
MAC Requirements
Equalization Sequences
Design Flow Steps
Customizing and Generating the Core
Targeted Supported Devices
Customizing the Core
Basic Tab
Advanced Settings Tab
Vivado IP Integrator Block Automation
Output Generation
Constraining the Core
Simulation
Synthesis and Implementation
Example Design
Generating Example Design
Simulating the Example Design
GT Selection and Pin Planning
GT Locations
Assigning GT Locations
GT Quad Locations
GT Selection and Pin Planning for Versal Premium
GT Locations
Assigning GT Locations
GT Quad Locations
Upgrading
Upgrading from UltraScale/UltraScale+ to Versal ACAP
Debugging
Finding Help on Xilinx.com
Documentation
Debug Guide
Answer Records
Master Answer Record for the Core
Technical Support
Debug Tools
Vivado Design Suite Debug Feature
Additional Resources and Legal Notices
Xilinx Resources
Documentation Navigator and Design Hubs
References
Revision History
Please Read: Important Legal Notices

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