Basic Tab - 1.0 English

The initial customization screen is used to define the basic parameters for the core, including the component name, reference clock frequency, lane width, and speed.

Figure 1. Basic Tab

Component Name

It is the base name of the output files generated for the core. The name must begin with a letter and can be composed of these characters: a to z, 0 to 9, and "_."

Link Width

The core requires the selection of the initial lane width. Supported lane widths are x1, x2, x4, x8, and x16.

Maximum Link Speed

The core allows you to select the Maximum Link Speed supported by the device. Supported link speeds are:

• 2.5 Gbps, 5.0 Gbps, 8.0 Gbps, and 16.0 Gbps. The 16.0 Gbps is available only for lane widths of x1, x2, x4, and x8.

Input Reference Clock Frequency

Selects the input frequency of the reference clock provided on sys_clk. It is the GT REFCLK frequency for the IP. Supported values are 100 MHz, 125 MHz, and 250 MHz. For important information about clocking, see Clocking.

Output User Clock Frequency

Selects the frequency of the output USERCLK that can be used by the PCIe MAC.

Table 1. User Clock Options with AMD PCIe MAC

Speed	Lane	User Clock (in MHz)
Gen1	x1	62.5, 125, 250
	x2	62.5, 125, 250
	x4	62.5, 125, 250
	x8	62.5, 125, 250
	x16	62.5, 125, 250
Gen2	x1	62.5, 125, 250
	x2	62.5, 125, 250
	x4	62.5, 125, 250
	x8	62.5, 125, 250
	x16	62.5, 125, 250
Gen3	x1	62.5, 125, 250
	x2	62.5, 125, 250
	x4	62.5, 125, 250
	x8	62.5, 125, 250
	x16	62.5, 125, 250, 500
Gen4	x1	125, 250
	x2	125, 250
	x4	125, 250
	x8	125, 250, 500

For important information about clocking the core, see Clocking.

Output Core Clock Frequency

Selects the frequency of the output coreclk that can be used by the PCIe MAC. 250 MHz is supported for all configurations. There is support for 500 MHz for x16 Gen3 (8.0 Gbps) and for x8 Gen4 (16.0 Gbps) configurations. For important information about clocking the core, see Clocking.

PLL Type

Selects the PLL type for GTs used. For all speed PCIe PHY IP uses LCPLL as PLL TYPE. But TXPROGDIV CLOCK SOURCE uses RPLL internally.

Table 2. PLL Type

Link Speed	PLL Type	Description
2.5 GT/s	LCPLL	The default is LCPLL.
5.0 GT/s	LCPLL	The default is LCPLL.
8.0 GT/s	LCPLL	The default is LCPLL.
16.0 GT/s	LCPLL	The default is LCPLL.