Clock and Rest Signals Interface Ports - 1.0 English

Versal Adaptive SoC PHY for PCI Express LogiCORE IP Product Guide (PG345)

Document ID
PG345
Release Date
2023-11-01
Version
1.0 English
Table 1. Clock and Reset Signals
Port Name Width I/O Clock Description
pcie_refclk 1 Input refclk Reference clock for fabric logic. The recommended reference clock is 100 MHz. This clock is expected to be free running and stable. This reference clock can be either synchronous or asynchronous. In synchronous mode, the PPM is 0. In asynchronous mode, the PPM is up to ±300 or 600 PPM worst case.The refclk differential pair are connected to the IBUFDS in the PHY IP. One of the IBUFDS_GTE5 outputs are connected to the soft modules in PHY_IP -(Phy_Wrapper). Other output is connected to the BUFG_GT. The BUFG_GT output (phy_gtrefclk) is used as a Reference clock for GT_Quads.
  • 100 MHz (default)
  • 125 MHz
  • 250 MHz
phy_gtrefclk 1 Input refclk Reference clock for GT_QUADS. This clock must be driven directly from an IBUFDS_GTE5. Same definition and frequency as phy_refclk.
sys_reset 1 Input Asynchronous When logic Low, this signal resets the PHY. This must be connected to PCIe PERST_N. Polarity is Active Low.
phy_coreclk 1 Output coreclk Core clock options:
  • 250 MHz
  • 500 MHz
phy_userclk 1 Output userclk User clock options:
  • 62.5 MHz
  • 125 MHz
  • 250 MHz
  • 500 MHz

phy_userclk is edge-aligned and phase-aligned to phy_coreclk.

phy_userclk2 1 Output userclk This clock is same as Core clock or user clock depending on the configuration. No user option is added at present. Not recommended to use.
phy_mcapclk 1 Output mcapclk This clock is same as phy_userclk. No user option is added at present. Not recommended to use.
phy_pclk 1 Output pclk Not configurable by user. Operations frequencies are:
  • 125 MHz: Gen1 operating speed
  • 250 MHz: Gen2 and Gen3 operating speed
  • 500 MHz: Gen4 operating speed

phy_pclk is edge-aligned, but not phase-aligned to phy_coreclk and phy_userclk.