Port Name | Width | I/O | Clock | Description |
---|---|---|---|---|
pcie_refclk | 1 | Input | refclk | Reference clock for fabric logic. The
recommended reference clock is 100 MHz. This clock is expected to be free running
and stable. This reference clock can be either synchronous or asynchronous. In
synchronous mode, the PPM is 0. In asynchronous mode, the PPM is up to ±300 or 600
PPM worst case.The refclk
differential pair are connected to the IBUFDS in the PHY IP. One of the
IBUFDS_GTE5 outputs are connected to the soft modules in PHY_IP -(Phy_Wrapper).
Other output is connected to the BUFG_GT. The BUFG_GT output (phy_gtrefclk) is
used as a Reference clock for GT_Quads.
|
phy_gtrefclk | 1 | Input | refclk | Reference clock for GT_QUADS. This clock must be driven directly from an IBUFDS_GTE5. Same definition and frequency as phy_refclk. |
sys_reset | 1 | Input | Asynchronous | When logic Low, this signal resets the PHY. This must be connected to PCIe PERST_N. Polarity is Active Low. |
phy_coreclk | 1 | Output | coreclk | Core clock options:
|
phy_userclk | 1 | Output | userclk | User clock options:
phy_userclk is edge-aligned and phase-aligned to phy_coreclk. |
phy_userclk2 | 1 | Output | userclk | This clock is same as Core clock or user clock depending on the configuration. No user option is added at present. Not recommended to use. |
phy_mcapclk | 1 | Output | mcapclk | This clock is same as phy_userclk. No user option is added at present. Not recommended to use. |
phy_pclk | 1 | Output | pclk | Not configurable by user. Operations frequencies are:
phy_pclk is edge-aligned, but not phase-aligned to phy_coreclk and phy_userclk. |