- The AMD Versal™ Adaptive SoC PHY for PCI Express® IP GTY can be configured to support PCIe® applications with 100 MHz, 125 MHz, or 250 MHz reference clock.
- The reference clock can be synchronous or asynchronous.
- The
phy_pclkis the primary clock for the PIPE interface, FPGA fabric, and GTY [TX/ RX]usrclkand [TX/RX]usrclk2. - In addition to
phy_pclk, there are other clocks (phy_coreclk,phy_userclk2,phy_userclk) available to support the PCIe MAC. -
BUFG_GTsare used to generate these clocks, so MMCM will not be required. - To use the reference clock for FPGA fabric, another
BUFG_GTmust be used. - The source of the GTY reference clock must come directly from IBUFDS_GTE5.
The following figure shows clocking architecture for the Versal adaptive SoC PCIe PHY IP configured for x2 lane width.
Figure 1. Clock Architecture
- PIPE_CLK (
phy_pclk) - Provided to Versal device GTY to clock
the PIPE interface. PIPE Clock must be 125 MHz for Gen1 operation or 250 MHz
for Gen2/Gen3 and 500 MHz for Gen4 operation. Note that the PIPE interface
data width is 16 bits for Gen1 or Gen2 operation, 32 bits for Gen3, and Gen4
operation. PIPE Clock frequency input to the block is switched dynamically
based on the current selected speed of operation is accomplished using a
BUFG_GTresource from the FPGA global clocking infrastructure.
- CORE_CLK (
phy_coreclk) - CORE_CLK is the dominant clock domain in the PCIe block,
core_clkis also used to drive UltraRAMs interfaced with the Hard Block.
- USER_CLK (
phy_userclk) - Clocks the non- AXI4 ST user interfaces. The frequency can be 62.5, 125, 250 or 500 MHz, depending on the data rate, number of lanes and Transaction Interface width.
- USER_CLK2 (
phy_userclk2) - Clocks the AXI4 ST user
interfaces. External to the block
user_clk2is the same as (and driven by the sameBUFG_GT) eithercore_clkoruser_clkdepending on the configuration. Internal to the blockuser_clk2is created usingcore_clkanduser_clk_enand similarly matches eithercore_clkoruser_clk.