Constraining the Core - 1.0 English

Versal Adaptive SoC PHY for PCI Express LogiCORE IP Product Guide (PG345)
Document ID
PG345
Release Date
2023-11-01
Version
1.0 English

This section contains information about constraining the core in the AMD Vivado™ Design Suite.

Required Constraints

The PCIe PHY IP solution requires the specification of timing and other physical implementation constraints to meet specified performance requirements. These constraints are provided in a Xilinx Design Constraints (XDC) file. Pin outs and hierarchy names in the generated XDC correspond to the provided example design.

Important: If the example design top file is not used, copy the IBUFDS_GTE5 instance for the reference clock, IBUF Instance for sys_rst, and also the timing constraints associated with them into your local design top.

You should provide the location constraint for sys_rst and sys_rst_override pins based on the development board in use. In addition, you should also provide GT location constraints.

In addition, you should also provide GT location constraints. For more information, see GT Selection and Pin Planning.

Constraints provided with the integrated block solution are tested in the hardware and provide consistent results. Constraints can be modified, but modifications should only be made with a thorough understanding of the effect of each constraint. Additionally, support is not provided for designs that deviate from the provided constraints.

Device, Package, and Speed Grade Selections

The device selection portion of the XDC informs the implementation tools which part, package, and speed grade to target for the design.

The device selection section always contains a part selection line, but can also contain part or package-specific options. An example part selection line follows:

CONFIG PART = XCVC1902-VSVA2197

Clock Frequencies

PHY IP GTH/GTY can be configured with 100 MHz, 125 MHz or 250 MHz reference clock frequency. Following is an example of constraining 100 MHz reference clock:
create_clock -name sys_clk -period 10 [get_ports sys_clk_p]

Clock Management

This section is not applicable for this IP core.

Clock Placement

Assign REFCLK package pin using package_pin constraints as shown in the following example:

set_property LOC GTY_REFCLK_X1Y4[get_cells -hierarchical -filter REF_NAME==IBUFDS_GTE5]

Assign sys_reset package pin using package_pin constraints as shown in the following example:

set_property IOSTANDARD LVCMOS18 [get_ports sys_rst_n]
set_property PACKAGE_PIN K35 [get_ports sys_rst_n]

Banking

This section is not applicable for this IP core.

Transceiver Placement

Assign GT location constraint. For x16 configuration 4 GT Quads need to be constrained. For x8 configuration 2 GT Quads need to be constrained. For x1, x2, and x4 configurations one GT Quad need to be constrained. Following is an example GT location constraints for x16 design:

set_property LOC GTY_QUAD_X1Y3 [get_cells $gt_quads -filter NAME=~*/gt_quad_3/*]
set_property LOC GTY_QUAD_X1Y2 [get_cells $gt_quads -filter NAME=~*/gt_quad_2/*]
set_property LOC GTY_QUAD_X1Y1 [get_cells $gt_quads -filter NAME=~*/gt_quad_1/*]
set_property LOC GTY_QUAD_X1Y0 [get_cells $gt_quads -filter NAME=~*/gt_quad_0/*]

I/O Standard and Placement

This section is not applicable for this IP core.