The following tables describe the supported PIPE signals by the PCIe PHY IP. For additional details, refer to the PIPE specification. The signals described in this section are based on a single lane application. Signals can be per-lane, or per-design. If not indicated in the description, the default is per-design. Per-design indicates that one signal controls all lanes (0 to N-1 Lane).
A per-lane signal on the PCIe PHY IP is in a form of {LaneN-1[Width-1:0], …Lane1 [Width-1:0], Lane0[Width-1:0]}.