phy_rx[p/n] |
1 |
Input |
Serial |
The differential receiver inputs to the PHY. Per-lane. |
phy_rxdata[63:0] |
64 |
Output |
pclk |
PIPE data output from receiver. Bits[63:32] are used for Gen5 and Gen4
and must be ignored in Gen1, Gen2, and Gen3. Bits[31:16] are used
for Gen3 only and must be ignored in Gen1 and Gen2.
Per-lane. |
phy_rxdatak[1:0] |
2 |
Output |
pclk |
Indicates whether RXDATA is control or data. Gen1 and Gen2 only.
Per-lane.
|
phy_rxdata_valid |
1 |
Output |
pclk |
This signal allows the PHY to instruct the MAC to
ignore RXDATA for one pclk cycle. When logic High, this indicates to
use RXDATA. When logic Low, this indicates to ignore RXDATA for one
pclk cycle. Gen3 and Gen4 only. Per-lane. |
phy_rxstart_block[1:0] |
2 |
Output |
pclk |
This signal allows the PHY to tell the MAC the starting byte for a
128b block.
- 00b: Data with no start
- 01b: A block starts at lower 32 bits
- 10b: A block starts at upper 32 bits,
inactive when operating at Gen3 speed.
- 11b: Illegal value when operating at Gen3
speed.
Gen3 and Gen4 only. Per-lane. |
phy_rxsync_header[1:0] |
2 |
Output |
pclk |
Provide the sync header for the MAC to use the next 128b block. The
MAC reads this value when the RXSTART_BLOCK is asserted. Gen3 and
Gen4 only. Per-lane. |