| phy_rxvalid |
1 |
Output |
pclk |
Indicates symbol lock and valid data on rxdata when logic High. This
signal must be ignored during reset and rate change Gen1 and Gen2 only.
Per-lane. |
| phy_phystatus |
1 |
Output |
pclk /Asynchronous |
Used to communicate completion of several PIPE
operations including reset, receiver detection, power management, and
rate change. Except for reset, this signal indicates done when asserted
for one pclk cycle. This signal is held High and asynchronous during
reset. In error situations, such as PHY not responding with PHYSTATUS,
the MAC should perform the necessary error recovery. Per-lane. |
| phy_phystatus_rst |
1 |
Output |
pclk /Asynchronous |
Similar to phystatus, except this port is used to
communicate completion of reset only. This signal is HIGH immediately
upon reset. After the PHY and GT resets are complete,this signal
transitions from High to Low. |
| phy_rxelecidle |
1 |
Output |
Asynchronous |
RXELECIDLE = High indicates RX electrical idle
detected. Gen1 and Gen2 only. Per-lane. |
| phy_rxstatus[2:0] |
3 |
Output |
pclk |
Encodes RX status and error codes for the RX data.
Per-lane.
- 000b: Received data OK
- 001b: 1 SKP added
- 010b: 1 SKP removed
- 011b: Receiver detected
- 100b: 8b/10b (Gen1/Gen2) or 128b/130b (Gen3/Gen4) decode error
- 101b: Elastic buffer overflow
- 110b: Elastic buffer underflow
- 111b: Receive disparity error (Gen1/Gen2)
|
| phy_ready |
1 |
Output |
Asynchronous |
Indicates Master Lane PHY GT is ready. |