Port Name | Width | I/O | Clock Domain | Description |
---|---|---|---|---|
phy_txdata[63:0] | 64 | Input | pclk | Parallel data input. Bits [63:32] are used for Gen5 and Gen4 only and must be ignored in Gen1, Gen2, and Gen3. Bits[31:16] are used for Gen3 only and must be ignored in Gen1 and Gen2. Per-lane. |
phy_txdatak[1:0] | 2 | Input | pclk | Indicates whether TXDATA is control or data for Gen1 and Gen2
only. Per-lane.
|
phy_txdata_valid | 1 | Input | pclk | This signal allows the MAC to instruct the PHY to ignore TXDATA for one PCLK cycle. When logic High, this indicates the PHY will use TXDATA. When logic Low, this indicates the PHY will not use TXDATA for one PCLK cycle. Gen3 and Gen4 only. Per-lane. |
phy_txstart_block | 1 | Input | pclk | This signal allows the MAC to tell the PHY the starting byte for a 128b block. The starting byte for a 128b block must always start at bit [0] of TXDATA. Gen3 and Gen4 only. Per-lane. |
phy_txsync_header[1:0] | 2 | Input | pclk |
Provide the sync header for the PHY to use the next 130b block. The PHY reads this value when the txstart_block is asserted. Gen3 and Gen4 only. Per-lane. |
phy_tx[p/n] | 1 | Output | Serial | The differential transmitter outputs. Per-lane. |