TX Equalization Interface Ports for Third-Party MAC - 1.0 English

Versal Adaptive SoC PHY for PCI Express LogiCORE IP Product Guide (PG345)
Document ID
PG345
Release Date
2023-11-01
Version
1.0 English

The Gen3/Gen4 TX and RX equalization defined here is different from the PIPE specification. The custom Gen3/Gen4 equalization scheme described here must be used for any third-party PCIe controllers. For more details, refer to Equalization Sequences.

Table 1. TX Equalization Signals for Gen3 and Gen4
Name Width I/O Clock Domain Description
phy_txeq_ctrl[1:0] 2 Input pclk TX equalization control. Must set back to 00b when txeq_done = 1b is detected. Gen3 and Gen4 speeds only. Per-lane.
  • 00b: Idle
  • 01b: TX preset
  • 10b: TX coefficient
  • 11b: TX query
phy_txeq_preset[3:0] 4 Input pclk Set the TX equalization to one of the defined preset when txeq_ctrl = 01b. Must use txeq_ctrl to change the preset, otherwise the default preset 0100b is used. Gen3 and Gen4 speeds only. Per-lane.
Preset Pre-shoot (dB) De-emphasis (dB)
0000b 0 6
0001b 0 3.5
0010b 0 4.5
0011b 0 2.5
0100b 0 0
0101b 2 0
0110b 2.5 0
0111b 3.5 6
1000b 3.5 3.5
1001b 3.5 0
1010b 0 9.5
Others Reserved
phy_txeq_coeff[5:0] 6 Input pclk Set the TX equalization to a custom coefficient when txeq_control = 10b. Three consecutive pclk cycles are required to register the new 18-bit TX coefficient.
  • The first pclk cycle is used to register pre-cursor.
  • The second pclk cycle is used to register main-cursor.
  • The third pclk cycle is used to register post-cursor.
Gen3 and Gen4 speeds only. Per-lane.
phy_txeq_fs[5:0] 6 Output pclk Indicates the full swing of the TX driver. Static value based on characteristics of TX driver. .Gen3 and Gen4 speeds only.
phy_txeq_lf[5:0] 6 Output pclk Indicates the low frequency of the TX driver. Static value based on characteristics of TX driver. Gen3 and Gen4 speeds only.
phy_txeq_new_coeff[17:0] 18 Output pclk Shows the status of the current TX equalization coefficient. Gen3 and Gen4 speeds only. Per-lane.
  • [17:12]: Pre-cursor.
  • [11:6]: Main-cursor.
  • [5:0]: Post-cursor.
phy_txeq_done 1 Output pclk This port is High when TXEQ is equalization done. Single cycle done indicator for txeq_control. Gen3 and Gen4 speeds only. Per-lane.
dbg_phy_txeq_fsm 3 Output pclk Tell TX EQ FSM state:

FSM_IDLE = 3’d0

FSM_PRESET = 3’d1

FSM_COEFF = 3’d2

FSM_REMAP = 3’d3

FSM_QUERY = 3’d4

FSM_DONE = 3’d5