This section describes the operation of the user-side Requester interface
associated with the 1024-bit AXI4-Stream
Interface.
The Requester interface enables a user Endpoint application to initiate
PCI transactions as a bus master across the
PCIe link to the host memory. For Root Complexes,
this interface is also used to initiate I/O and configuration requests. This interface
can also be used by both Endpoints and Root Complexes to send messages on the PCIe link. The transactions on this interface are similar
to those on the completer interface, except that the roles of the core and the user
application are reversed. Posted transactions are performed as single indivisible
operations and Non-Posted transactions as split transactions.
The requester interface consists of two separate interfaces, one for data
transfer in each direction. Each interface is based on the
AXI4-Stream protocol, and its width can be configured as 64, 128 or 256
bits. The requester request interface is used for transfer of requests (with any
associated payload data) from the user application to the core, and the requester
completion interface is used by the core to deliver Completions received from the link
(for Non-Posted requests) to the user application. The two interfaces operate
independently, that is, the user application can transfer new requests over the
requester request interface while receiving a completion for a previous request.
Note: All signals in the waves are not appended with
pcie0 or pcie1 ports, but apply to both pcie0* and pcie1* ports.