The following figure illustrates the signals associated with the completer request interface of the core. The core delivers each TLP on this interface as an AXI4-Stream packet. The packet starts with a 128-bit descriptor, followed by data in the case of TLPs with a payload.
The completer request interface supports two distinct data alignment modes, selected during core customization in the AMD Vivado™ IDE. In the Dword-aligned mode, the first byte of valid data appears in lane n = S + 16 + (A mod 4) mod 64, where A is the byte-level starting address of the data block being transferred and S is the lane number where the first byte of the descriptor appears. For messages and Configuration Requests, the address A is taken as 0. The starting lane number S is always 0 when the straddle option is not used, but can be 0 or 32 when straddle is enabled.
In the 128-bit address-aligned mode, the start of the payload on the 1024-bit bus is always aligned on a 128-bit boundary. However the start of the descriptor on the 1024-bit bus is always aligned to byte 0 or byte 32 only. The byte offset corresponding to the first byte of the payload is determined as n = (S + 16 + (A mod 16)) mod 64, where S is the byte offset where the first byte of the descriptor appears (which can be 0, 32, 64 or 96) and A is the memory or I/O address corresponding to the first byte of the payload.
Any gap between the end of the descriptor and the start of the first byte of the payload is filled with null bytes.
The interface also supports a straddle option that allows the transfer of up to two TLPs in the same beat across the interface. The straddle option can be used only with the Dword-aligned mode, and is not supported when using the 128-bit address aligned mode. The descriptions in the next sections assume a single TLP per beat. The operation of the interface with the straddle option enabled is described in Straddle Option on CQ Interface.