Configuration Control Interface - 3.4 English

Versal Adaptive SoC CPM Mode for PCI Express Product Guide (PG346)
Document ID
PG346
Release Date
2023-11-20
Version
3.4 English

The configuration control interface signals allow a broad range of information exchange between the user application and the core. The user application uses this interface to do the following:

  • Set the configuration space.
  • Indicate if a correctable or uncorrectable error has occurred.
  • Set the device serial number.
  • Set the downstream bus, device, and function number.
  • Receive per function configuration information.

This interface also provides handshaking between the user application and the core when a Power State change or function level reset occurs.

Note: The pcie0* signals map to PCIe Controller 0 and pcie1* signals map to PCIe Controller 1 in the port descriptions below.
Table 1. Configuration Control Interface Port Descriptions
Port I/O Width Description

pcie0_cfg_control_hot_reset_in

pcie1_cfg_control_hot_reset_in		 I 1

Configuration Hot Reset In

In RP mode, assertion transitions LTSSM to hot reset state, active-High.

pcie0_cfg_control_hot_reset_out

pcie1_cfg_control_reset_out		 O 1

Configuration Hot Reset Out

In EP mode, assertion indicates that EP has transitioned to the hot reset state, active-High.

pcie0_cfg_control_power_state_change_ack

pcie1_cfg_control_power_state_change_ack		 I 1

Configuration Power State Ack

You must assert this input to the core for one cycle in response to the assertion of pcie(n)_cfg_control_power_state_change_interrupt, when it is ready to transition to the low-power state requested by the configuration write request. The user application can permanently hold this input High if it does not need to delay the return of the completions for the configuration write transactions, causing power-state changes.

pcie0_cfg_control_power_state_change_interrupt

pcie1_cfg_control_power_state_change_interrupt

 O 1

Power State Change Interrupt

The core asserts this output when the power state of a physical or virtual function is being changed to the D1 or D3 states by a write into its Power Management Control register. The core holds this output High until the user application asserts the pcie(n)_cfg_control_power_state_change_ack input to the core. While pcie(n)_cfg_control_power_state_change_interrupt remains High, the core does not return completions for any pending configuration read or write transaction received by the core. The purpose is to delay the completion for the configuration write transaction that caused the state change until the user application is ready to transition to the low-power state. When pcie(n)_cfg_control_power_state_change_interrupt is asserted, the function number associated with the configuration write transaction is provided on the pcie(n)_cfg_ext_function_number[7:0] output. When the user application asserts pcie(n)_cfg_control_power_state_change_ack, the new state of the function that underwent the state change is reflected on pcie(n)_cfg_status_function_power_state (for PFs) or the pcie(n)_cfg_status_vf_power_state (for VFs) outputs of the core.

pcie0_cfg_control_err_cor_in

pcie1_cfg_control_err_cor_in		 I 1

Correctable Error Detected

The user application activates this input for one cycle to indicate a correctable error detected within the user logic that needs to be reported as an internal error through the PCI Express Advanced Error Reporting (AER) mechanism. In response, the core sets the Corrected Internal Error Status bit in the AER Correctable Error Status register of all enabled functions, and also sends an error message if enabled to do so. This error is not considered function-specific.

pcie0_cfg_control_err_uncor_in

pcie1_cfg_control_err_uncor_in		 I 1

Uncorrectable Error Detected

The user application activates this input for one cycle to indicate a uncorrectable error detected within the user logic that needs to be reported as an internal error through the PCI Express Advanced Error Reporting mechanism. In response, the core sets the uncorrected Internal Error Status bit in the AER Uncorrectable Error Status register of all enabled functions, and also sends an error message if enabled to do so. This error is not considered function-specific.

pcie0_cfg_control_flr_done

pcie1_cfg_control_flr_done		 I

4 in CPM4

1 in CPM5

Function Level Reset Complete in CPM4

The user application must assert this input when it has completed the reset operation of the Virtual Function. This causes the core to deassert pcie(n)_cfg_control_flr_in_process for physical function i and to re-enable configuration accesses to the physical function. The core will issue CRS to configurations requests to a particular Physical Function till pcie(n)_cfg_control_flr_done is not asserted when pcie(n)_cfg_control_flr_in_process =1 for that Physical Function.

Function Level Reset Complete in CPM5

The user application must assert this input when it has completed the reset operation of the cfg_flr_done_func_num Function that received a CfgWr TLP writing a 1 to Function Level Reset. This causes the core to re-enable configuration accesses to the Function.

pcie0_cfg_control_vf_flr_done

pcie1_cfg_control_vf_flr_done		 I 1

Function Level Reset for Virtual Function is Complete

The user application must assert this input when it has completed the reset operation of the Virtual Function. This causes the core to deassert pcie(n)_cfg_control_vf_flr_in_process for function i and to re-enable configuration accesses to the virtual function. The core will issue CRS to configuration requests to a particular Virtual Function till pcie(n)_cfg_control_vf_flr_done is not asserted when pcie(n)_cfg_control_vf_flr_in_process = 1 for that Virtual Function.
Note: Port is not present in CPM5.

pcie0_cfg_control_vf_flr_func_num

pcie1_cfg_control_vf_flr_func_num		 I 8

Function Level Reset for Virtual Function i is Complete.

This user application drives a valid Virtual Function number on this input along with asserting pcie(n)_cfg_control_vf_flr_done when the reset operation of Virtual Function i completes.

Valid entries are 8'h04-8'hFF for VF0-VF251. Values 8'h00-8'h03 are reserved.
Note: Port is not present in CPM5.

pcie0_cfg_control_flr_in_process

pcie1_cfg_control_flr_in_process

 O 4

Function Level Reset In Process

The core asserts bit i of this bus when the host initiates a reset of physical function i through its FLR bit in the configuration space. The core continues to hold the output High until the user sets the corresponding pcie(n)_cfg_control_flr_done input for the corresponding physical function to indicate the completion of the reset operation.
Note: Port is not present in CPM5.

pcie0_cfg_control_vf_flr_in_process

pcie1_cfg_control_vf_flr_in_process		 O 252

Function Level Reset In Process for Virtual Function

The core asserts bit i of this bus when the host initiates a reset of virtual function i though its FLR bit in the configuration space. The core continues to hold the output High until the user sets the pcie(n)_cfg_control_vf_flr_done input and drives pcie(n)_cfg_control_vf_flr_func_num with the corresponding function to indicate the completion of the reset operation.
Note: Port is not present in CPM5.

pcie0_cfg_control_flr_done_func_num

pcie1_cfg_control_flr_done_func_num

 I 16

Function Level Reset Done Interface.

Valid entries 16'h0000-16'h100F for Function IDs from 0 to 15 (PFs) and 16 to 4111 (VFs) with cfg_flr_done driven to 1. Values 16'h1010-16'hFFFF are reserved.