The configuration interrupt controller interface allows the user application to set Legacy PCIe interrupts, MSI interrupts, or MSI-X interrupts. The core provides the interrupt status on the configuration interrupt sent and fail signals. The following tables define the interface ports associated with the configuration interrupt controller interface of the core.
Note: The
pcie0* signals map to PCIe
Controller 0 and pcie1* signals map to PCIe Controller 1 in the port descriptions below.