The configuration status interface provides information on how the core is configured, such as the negotiated link width and speed, the power state of the core, and configuration errors. The following table defines the ports in the configuration status interface of the core.
pcie0* signals map to PCIe
Controller 0 and pcie1* signals map to PCIe Controller 1 in the port descriptions below.| Port | I/O | Width | Description |
|---|---|---|---|
| pcie0_cfg_status_cq_np_req_count pcie1_cfg_status_cq_np_req_count | O | 6 | This output provides the current value of the
credit count maintained by the core for delivery of Non-Posted
requests to the user logic. The core delivers a Non-Posted request
across the completer request interface only when this credit count
is non-zero. This counter saturates at a maximum limit of 32. Because of internal pipeline delays, there can be several cycles of delay between the user application providing credit on the pcie_cfg_status_cq_np_req[1:0] inputs and the PCIe core updating the pcie_cfg_status_cq_np_req_count output in response. This count resets on user_reset and deassertion of user_lnk_up. |
|
pcie0_cfg_status_cq_np_req |
I | 2 | This input is used by the user application to
request the delivery of a Non-Posted request. The core implements a
credit-based flow control mechanism to control the delivery of
Non-Posted requests across the interface, without blocking Posted
TLPs. This input to the core controls an internal credit count. The credit count is updated in each clock cycle based on the setting of pcie_cfg_status_cq_np_req[1:0] as follows:
The credit count is decremented on the delivery of each Non-Posted request across the interface. The core temporarily stops delivering Non-Posted requests to the user logic when the credit count is zero. It continues to deliver any Posted TLPs received from the link even when the delivery of Non-Posted requests has been paused. The user application can either set pcie_cfg_status_cq_np_req[1:0] in each cycle based on the status of its Non-Posted request receive buffer, or can set it to 11 permanently if it does not need to exercise selective backpressure on Non-Posted requests. The setting of pcie_cfg_status_cq_np_req[1:0] does not need to be aligned with the packet transfers on the completer request interface. |
| pcie0_cfg_status_phy_link_down pcie1_cfg_status_phy_link_down | O | 1 | Configuration link down Status of the PCI Express link based on the Physical Layer LTSSM.
Note: Per the PCI
Express Base Specification, rev. 3.0, LinkUp is 1b in the
Recovery, L0, L0s, L1, and L2 cfg_status_ltssm states. In the
configuration state, LinkUp can be 0b or 1b. It is always 0b
when the configuration state is reached using . LinkUp is 1b if the configuration state is
reached through any other state transition.
Note: While reset is asserted, the output of this
signal are 0b until reset is released.
|
| pcie0_cfg_status_phy_link_status pcie1_cfg_status_phy_link_status | O | 2 | Configuration Link Status Status of the PCI Express link.
|
| pcie0_cfg_status_negotiated_width pcie1_cfg_status_negotiated_width | O | 3 | Negotiated Link Width This output indicates the negotiated width of the given PCI Express Link and is valid when cfg_status_phy_link_status[1:0] == 11b (DL Initialization is complete). Negotiated Link Width values:
|
| pcie0_cfg_status_current_speed pcie1_cfg_status_current_speed | O |
2 for CPM4 3 for CPM5 |
Current Link Speed This signal outputs the current link speed of the given PCI Express Link.
|
|
pcie0_cfg_status_max_payload pcie1_cfg_status_max_payload |
O | 2 | Max_Payload_Size This signal outputs the maximum payload size from Device Control register bits 7 down to 5. This field sets the maximum TLP payload size. As a Receiver, the logic must handle TLPs as large as the set value. As a Transmitter, the logic must not generate TLPs exceeding the set value.
|
|
pcie0_cfg_status_max_read_req pcie1_cfg_status_max_read_req |
O | 3 | Max_Read_Request_Size This signal outputs the maximum read request size from Device Control register bits 14 down to 12. This field sets the maximum Read Request size for the logic as a Requester. The logic must not generate Read Requests with size exceeding the set value.
|
|
pcie0_cfg_status_function_status pcie1_cfg_status_function_status |
O |
16 for CPM4 4 for CPM5 |
Configuration Function Status These outputs indicate the states of the Command register bits in the PCI configuration space of each function. These outputs are used to enable requests and completions from the host logic. The assignment of bits is as follows:
Note: In CPM5, only the
Function 0 state is indicated. For subsequent functions, the
wrreq interface is used.
|
|
pcie0_cfg_status_vf_status |
O | 504 |
For CPM4 Configuration Virtual Function Status These outputs indicate the status of virtual functions, two bits each per virtual function.
For CPM5 This pin is not available and unused, use wrreq interface instead. |
| pcie0_cfg_status_function_power_state pcie1_cfg_status_function_power_state |
O |
12 in CPM4 3 in CPM5 |
Configuration Function Power State These outputs indicate the current power state of the physical functions. Bits [2:0] capture the power state of function 0, and bits [5:3] capture that of function 1, and so on. The possible power states are:
Note: In CPM5, only the
Function 0 power state is indicated. For subsequent functions,
the wrreq interface is used.
|
| pcie0_cfg_status_vf_power_state pcie1_cfg_status_vf_power_state | O | 756 |
For CPM4 Configuration Virtual Function Power State These outputs indicate the current power state of the virtual functions. Bits [2:0] capture the power state of virtual function 0, and bits [5:3] capture that of virtual function 1, and so on. The possible power states are:
For CPM5 This pin is not available and unused, use wrreq interface instead. |
| pcie0_cfg_status_link_power_state pcie1_cfg_status_link_power_state | O | 2 | Current power state of the PCI Express link, and is valid when
cfg_status_phy_link_status[1:0] == 11b (DL Initialization is
complete).
|
| pcie0_cfg_status_local_error_out pcie1_cfg_status_local_error_out | O | 5 | Local Error Conditions: Error priority is noted
and Priority 0 has the highest priority.
|
| pcie0_cfg_status_local_error_valid pcie1_cfg_status_local_error_valid | O | 1 | Local Error Conditions Valid: Block activates
this output for one cycle when any of the errors in
cfg_status_local_error_out[4:0] are encountered. When driven 1b
cfg_status_local_error_out[4:0] indicates local error type. Priority
of error reporting (for the case of concurrent errors) is
noted. Note: This signal might not work for all PCIe link width/speed
configurations. Do not rely solely on this signal to indicate an
error. Alternatively, you can decode AER register to accurately
detect errors.
|
| pcie0_cfg_status_rx_pm_state pcie1_cfg_status_rx_pm_state | O | 2 | Current RX Active State Power Management L0s
State: Encoding is listed below and valid when
cfg_status_ltssm_state is indicating L0:
|
| pcie0_cfg_status_tx_pm_state pcie1_cfg_status_tx_pm_state | O | 2 | Current TX Active State Power Management L0s
State: Encoding is listed below and valid when
cfg_status_ltssm_state is indicating L0:
|
| pcie0_cfg_status_ltssm_state pcie1_cfg_status_ltssm_state | O | 6 | LTSSM State. Shows the current LTSSM state:
|
|
pcie0_cfg_status_rcb_status pcie1_cfg_status_rcb_status |
O |
4 in CPM4 1 in CPM5 |
RCB Status. Provides the setting of the Read Completion Boundary (RCB) bit in the Link Control register of each physical function. In Endpoint mode, bit 0 indicates the RCB for Physical Function 0 (PF 0), bit 1 indicates the RCB for PF 1, and so on. In RC mode, bit 0 indicates the RCB setting of the Link Control register of the RP, bit 1 is reserved. For each bit, a
value of 0 indicates an RCB of 64 bytes and a value of 1
indicates 128 bytes.
Note: In CPM5, only the Function 0 setting is indicated. For
subsequent functions, the wrreq interface is
used.
|
| pcie0_cfg_status_pl_status_change pcie1_cfg_status_pl_status_change | O | 1 | This output is used by the core in Root Port
mode to signal one of the following link training-related events:
The pl_interrupt output is not active when the core is configured as an Endpoint. |
|
pcie0_cfg_status_ext_tag_enable pcie1_cfg_status_ext_tag_enable |
O | 1 | Extended Tag Enable:Per function state of Device Control Register Ext Tag (8-Bit) Enable bit. |
| pcie0_cfg_status_atomic_requester_enable pcie1_cfg_status_atomic_requester_enable |
O |
4 in CPM4 1 in CPM5 |
Atomic Operation Requester Enable: Per function
state of Device Control2 Register AtomicOp Requester Enable
bit. Note: In CPM5, only
the Function 0 state is indicated. For subsequent functions, the
wrreq interface is used.
|
|
pcie0_cfg_status_10b_tag_requester_enable pcie1_cfg_status_10b_tag_requester_enable |
O |
4 in CPM4 1 in CPM5 |
10b Tag Requester Enable: Per function state of
Device Control2 Register 10-Bit Tag Requester Enable bit. Note: In CPM5, only the
Function 0 state is indicated. For subsequent functions, the
wrreq interface is used.
|
|
pcie0_cfg_status_rq_tag_av |
O | 4 | This output provides an indication of the number
of free tags available for allocation to Non-Posted requests on the
PCIe master side of the
core. The user logic checks this output before transmitting a
Non-Posted request on the requester request interface, to avoid
blocking the interface when no tags are available. The encodings
are:
Because of pipeline delays, the value on this output does not include the tags consumed by the Non-Posted requests sent by the user logic in the last 8 clock cycles or less. The user logic must adjust the value on this output by the number of Non-Posted requests it sent in the previous clock cycles, if any. |
|
pcie0_cfg_status_rq_tag_vld0 pcie1_cfg_status_rq_tag_vld0 |
1 | O | The core asserts this output for one cycle when
it has allocated a tag to an incoming Non-Posted request from the
requester request interface and placed it on the
pcie(n)_cfg_status_rq_tag0 output. The bit is encoded as follows:
|
|
pcie0_cfg_status_rq_tag_vld1 pcie1_cfg_status_rq_tag_vld1 |
1 | O | The core asserts this output for one cycle when
it has allocated a tag to an incoming Non-Posted request from the
requester request interface and placed it on the
pcie(n)_cfg_status_rq_tag1 output. The bit is encoded as follows:
|
|
pcie0_cfg_status_rq_tag0 pcie1_cfg_status_rq_tag0 |
20 | O | When tag management for Non-Posted requests is performed by the core
(Enable Client Tag is unchecked in the IP customization GUI), this
output is used by the core to communicate the allocated tag for each
Non-Posted request received from the client. The tag value on
pcie(n)_cfg_status_rq_tag0 is valid for one cycle when
pcie(n)_cfg_status_rq_tag_vld0 is High. The client must copy this
tag and use it to associate the completion data with the pending
request. There can be a delay of several cycles between the transfer of the request on the pcie(n)_s_axis_rq_tdata bus and the assertion of pcie(n)_cfg_status_rq_tag_vld0 by the core to provide the allocated tag for the request. The client can, meanwhile, continue to send new requests. The tags for requests are communicated on this bus in FIFO order. Therefore, the user application must associate the allocated tags with the requests in the order in which the requests were transferred over the interface. When pcie(n)_cfg_status_rq_tag0 and pcie(n)_cfg_status_rq_tag1 are both valid in the same cycle, the value on pcie(n)_cfg_status_rq_tag0 corresponds to the earlier of the two requests transferred over the interface. |
|
pcie0_cfg_status_rq_tag1 pcie1_cfg_status_rq_tag1 |
20 | O | The description of this signal is the same as pcie(n)_cfg_status_rq_tag0, except the tag value on pcie(n)_cfg_status_rq_tag1 is valid for one cycle when pcie(n)_cfg_status_rq_tag_vld1 is asserted. |
| pcie0_cfg_status_rq_seq_num0 pcie1_cfg_status_rq_seq_num0 | 6 | O | You might optionally use this output to keep
track of the progress of the request in the core's transmit
pipeline. To use this feature, the user application must provide a
sequence number for each request on the
pcie(n)_cfg_status_rq_seq_num0[5:0] bus. The core outputs this
sequence number on the pcie(n)_cfg_status_rq_seq_num0[5:0] output
when the request TLP has progressed to a point in the pipeline where
a Completion TLP from the client will not be able to pass it. This
mechanism enables the client to maintain ordering between
Completions sent to the completer completion interface of the core
and Posted requests sent to the requester request interface. Data on the pcie(n)_cfg_status_rq_seq_num0[5:0] output is valid when pcie(n)_cfg_status_rq_seq_num_ vld0 is high. |
| pcie0_cfg_status_rq_seq_num1 pcie1_cfg_status_rq_seq_num1 | 6 | O | This output is identical in function to that of
pcie(n)_cfg_status_rq_seq_num0. It is used to provide a second
sequence number in the same cycle when a first sequence number is
being presented on pcie(n)_cfg_status_rq_seq_num0. Data on the pcie(n)_cfg_status_rq_seq_num1[5:0] output is valid when pcie(n)_cfg_status_rq_seq_num_vld1 is High. |
| pcie0_cfg_status_rq_seq_num_vld0 pcie1_cfg_status_rq_seq_num_vld0 | 1 | O | This output is asserted by the core for one cycle when it has placed valid data on pcie(n)_cfg_status_rq_seq_num0[5:0]. |
| pcie0_cfg_status_rq_seq_num_vld1 pcie1_cfg_status_rq_seq_num_vld1 | 1 | O | This output is asserted by the core for one cycle when it has placed valid data on pcie(n)_cfg_status_rq_seq_num1[5:0]. |