Configuring the CIPS IP Core - 3.4 English

Versal Adaptive SoC CPM Mode for PCI Express Product Guide (PG346)
Document ID
PG346
Release Date
2023-11-20
Version
3.4 English
  1. In the Vivado IDE, select IP Integrator > Create Block Design from the Flow Navigator, as shown in the following figure.


    A pop-up dialog displays to create the block design.

  2. Click OK. An empty block design diagram canvas opens in the IP integrator.
  3. Right-click on the block design canvas and from the context menu select Add IP.
  4. Search for cips.


  5. Double-click the Control, Interface, and Processing System IP core to customize it.
  6. In the Configuration Options pane, leave the settings as default or select appropriate options required for presets and click Next.
    Note: For information about the option presets, see Control, Interface and Processing System LogiCORE IP Product Guide (PG352).
  7. Click the CPM block to configure the core.

    The CPM Basic Configuration page displays.

  8. Set the PCIe Controller 0 Mode to PCIE, and select the lane width. This setting enables the PCIe Port 0, and in a later step, you will be configuring the PCIe Port 0.
  9. If you require the PCIe Port 1, set the PCIe Controller 1 Mode to PCIE, and select the lane width.
    Table 1. Available Lane Width Combinations
    PCIe Port 0 PCIe Port 1
    X1, X2, X4, or X8 X1, X2, X4, or X8
    X16 Not available
    Note: PCIe Port 1 is available only if the lane width of PCIe Port 0 is less than or equal to X8.
    Note: PCIe Port 1 supports up to X8 when PCIe Port 0 is configured up to X8.
  10. In the Configuration Options pane, expand CPM5, and click PCIE Controller 0 Configuration to customize the PCIe Port 0 for the Versal adaptive SoC CPM Mode for PCI Express core. It offers two modes: Basic, and Advanced. To select a mode, use the CPM Modes drop-down list on the first page of the Customize IP dialog box. Next section will explain the parameters available in each mode.
  11. If applicable, in the Configuration Options pane, expand CPM, and click PCIE Controller 1 Configuration to customize PCIe Port 1.
  12. After configuring the PCIe controller, click OK to return to the Configure screen, as shown below.
  13. Click PS PMC, and click IO configuration.

    The IO Configuration tab has a list of options to configure the external PCIe Reset options.

  14. Select the PCIe Reset option located in the Peripheral column.

    Notice that the MIO pin selected in the PCIe reset is automatically connected to the PCIe reset I/O. In the figure below, MIO 38 is connected to the PCIe reset I/O.

    1. For PCIe Port 0 Endpoint configuration: Next to A0 Endpoint, select one of the available MIOs: PS MIO 18, PMC MIO 24, or PMC MIO 38. This selection should match the MIO that is connected to the PCIe reset I/O in the board schematic. In the figure below, PMC MIO 38 is selected to correspond to PCIe reset MIO 38.
    2. If PCIe Port 1 is enabled: Next to A1 Endpoint, select one of the available MIOs (PS MIO 19, PMC MIO 25, or PMC MIO 39) based on which MIO is connected to the PCIe reset I/O in the board schematic.
  15. If the board will boot from serial NOR flash, select the a QSPI or OSPI option in Boot Mode options to enable programming of the flash on the board. Select the appropriate option based on availability to match the board schematic.

    To set up the boot device, see the Versal Adaptive SoC Technical Reference Manual (AM011). If a serial NOR flash boot device will be used, the correct option must be selected to enable the correct MIOs.

  16. To enable additional I/O interfaces, such as UART, 12C, and USB IOs, select them in the Peripherals section in a similar manner. See the Versal Adaptive SoC Technical Reference Manual (AM011) for more details on these interfaces.