PASID
PASID Extended Capability structure has been added which can be enabled via GUI with which the core supports sending and receiving TLPs containing a PASID TLP Prefix.10-Bit Tag
The CPM5 PCIe controller supports 10-bit Tag feature, it inherently supports 10-bit tag on the completer interface while requester interface can be enabled via GUI option. When enabled management of up to 768 tags is possible compared to max of 256 tags in UltraScale+ devices.
Feature DLLP
Data Link Feature Extended Capability structure has been added for link speed of 16.0 GT/s and 32.0 GT/s. It contains programmable control/status information about the local and peer support of the Data Link Feature Support.
Lane Margining
Lane margining at the receiver extended capability structure is added for link speed of 16.0 GT/s and 32.0 GT/s.
Physical Layer 16.0 GT/s Extended Capability
Physical Layer 16.0 GT/s Extended Capability structure has been added for link speed of 16.0 GT/s with which Gen4 equalization status can be read.
Physical Layer 32.0 GT/s Extended Capability
Physical Layer 32.0 GT/s extended capability structure is added for link speed of 32.0 GT/s with which Gen5 equalization status can be read.
Retimers Supported
Link extension device (retimers) is supported to inter operate with CPM5 PCIe block for link speed of 16.0 GT/s and above.
Flow Control Informational Select
All combinations of cfg_fc_sel values are supported relative to UltraScale+, refer port description for more details.
Physical and Virtual Functions
The CPM5 PCIe controller supports up to 16 Physical functions and 4080 Virtual functions as compared to 4 Physical and 252 Virtual Functions in UltraScale+.
MSIX – Additional Vectors
When configured as MSIX-internal can support up to 2k vectors per physical function compared to 8 in UltraScale+, vectors per function for VF and total number of vectors increases to 32k accordingly.
Switch Mode
CPM5 PCIe controller can be configured as upstream or downstream port of a switch design.