Illustrative Example of Basic Bus Mastering Endpoint
By far the most common use of the Versal Adaptive SoC CPM Mode for PCI Express is to construct a bus mastering Endpoint using a CPM PCIe controller. This use model is applicable to most applications that interface the Endpoint port on a Versal device (on an add-in card) to a root complex or switch downstream port through a PCI Express connector. The following figure shows a block diagram of the bus mastering Endpoint use case.
PCI Express Two Function Endpoint
The following figure shows the architecture of a two-function Endpoint design. The CPM PCIe Controller is configured to enable two built-in function configuration spaces. This use case enables the application device driver to access and control two distinct applications independently. The user logic implements the DMA, control registers and applications.
PCI Express Endpoint with SR-IOV
The following figure shows the CPM PCIe Controller configured as a SR-IOV capable Endpoint, interfacing with the user design. This use case addresses requirements for up to four physical and 252 virtual functions, and minimizes the soft logic requirement to implement an SR-IOV Endpoint.
PCI Express Endpoint with AXI4 Memory Mapped Interface
This use case describes a PCI Express Endpoint functional unit that implements AXI4 (AXI4) interfaces. This functional block implements a soft logic bridge between the native AXI4-Stream interface on the CPM PCIe controller and AXI4 interconnect.
PCI Express Endpoint Using Tandem PROM
This use case addresses the ability to configure Versal device in two stages and bring up the PCI Express protocol in less than 100 ms after power to the Versal device is stable. This is accomplished through a staged configuration flow.
PCI Express Endpoint Using Tandem PCIe
This use case addresses the ability to initially load fully configurable PCI Express protocol solution from a small external ROM, so as to meet the 100 ms configuration requirement. A PCIe link is formed with a Root Complex or Switch component, which is subsequently used to download the design that configures the rest of the Versal device. In this case the PCIe link is used by the user application. This is accomplished through a staged configuration flow.