The previous figure illustrates the signals associated with the requester completion interface of the core. When straddle is not enabled, the core delivers each TLP on this interface as an AXI4-Stream packet. The packet starts with a 96-bit descriptor, followed by data in the case of Completions with a payload.
The requester completion interface supports two distinct data alignment modes
for transferring payloads, which are during core customization in the AMD Vivado™
IDE. In the Dword-aligned mode, the core
transfers the first Dword of the Completion payload immediately after the last Dword of
the descriptor. In the 128-bit address aligned mode, the core starts the payload
transfer in the second 128-bit quarter of the 1024-bit word, following the descriptor in
the first quarter. The first Dword of the payload can be in any of the four possible
Dword positions in the second quarter, and its offset f the is determined by address
offset provided by the user logic when it sent the request to the core (that is, the
setting of the addr_offset input of the requester
request interface). Thus, the 128-bit address aligned mode can be used on the requester
completion interface only if the requester request interface is also configured to use
the 128-bit address aligned mode.