The following tables are the translation tables for AXI4-Stream and memory-mapped transactions.
|AXI4 Memory-Mapped Transaction||AXI4-Stream PCIe TLPs|
|INCR Burst Read of AXIBAR||MemRd 32 (3DW)|
|INCR Burst Write to AXIBAR||MemWr 32 (3DW)|
|INCR Burst Read of AXIBAR||MemRd 64 (4DW)|
|INCR Burst Write to AXIBAR||MemWr 64 (4DW)|
|AXI4-Stream PCIe TLPs||AXI4 Memory-Mapped Transaction|
|MemRd 32 (3DW) of PCIEBAR||INCR Burst Read|
|MemWr 32 (3DW) to PCIEBAR||INCR Burst Write|
|MemRd 64 (4DW) of PCIEBAR||INCR Burst Read|
|MemWr 64 (4DW) to PCIEBAR||INCR Burst Write|
For PCIe® requests with lengths greater than 1 Dword, the size of the data burst on the Master AXI interface will always equal the width of the AXI data bus even when the request received from the PCIe link is shorter than the AXI bus width.
s_axi_wstrb can be used to facilitate data alignment to an address boundary.
s_axi_wstrb may equal 0 in the beginning of a valid data cycle
and will appropriately calculate an offset to the given address. However, the valid
data identified by
s_axi_wstrb must be continuous from the first
byte enable to the last byte enable.