AXI4 Memory Mapped Interface - 3.4 English

Versal Adaptive SoC CPM DMA and Bridge Mode for PCI Express Product Guide (PG347)

Document ID
PG347
Release Date
2023-11-20
Version
3.4 English

AXI4 (MM) Master ports are connected from the CPM to the AMD Versal device Network on Chip (NoC) internally. For details, see Versal Adaptive SoC Programmable Network on Chip and Integrated Memory Controller LogiCORE IP Product Guide (PG313). The AXI4 Master interface can be connected to DDR or to the PL user logic, depending on the NoC configuration.