AXI4 Memory Mapped Interface - 3.3 English

Versal ACAP CPM DMA and Bridge Mode for PCI Express Product Guide (PG347)

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3.3 English

AXI4 Memory Mapped (MM) Master ports are connected from the CPM to the Versal ACAP Network on Chip (NoC) internally. For details, see Versal ACAP Programmable Network on Chip and Integrated Memory Controller LogiCORE IP Product Guide (PG313). The AXI4 MM Master interface can be connected to DDR or to the PL user logic, depending on the NoC configuration.