AXI4-Stream C2H Completion Ports - 3.4 English

Versal Adaptive SoC CPM DMA and Bridge Mode for PCI Express Product Guide (PG347)

Document ID
PG347
Release Date
2023-11-20
Version
3.4 English
Table 1. AXI4-Stream C2H Completion Port Descriptions
Port Name I/O Description
dma<n>_s_axis_c2h_cmpt_data[511:0] I Completion data from the user application. This contains information that is written to the completion ring in the host.
dma<n>_s_axis_c2h_cmpt_size [1:0] I 00: 8B completion.

01: 16B completion.

10: 32B completion.

11: 64B completion

dma<n>_s_axis_c2h_cmpt_dpar [15:0] I

Odd parity computed as bit per 32b.

dma<n>_s_axis_c2h_cmpt_dpar[0] is parity over dma<n>_s_axis_c2h_cmpt_data[31:0].

dma<n>_s_axis_c2h_cmpt_dpar[1] is parity over dma<n>_s_axis_c2h_cmpt_data[63:31] and so on.

dma<n>_s_axis_c2h_cmpt_ctrl_qid[10:0] I Completion queue ID.
dma<n>_s_axis_c2h_cmpt_ctrl_marker I Marker message used for making sure pipeline is completely flushed. After that, you can safely do queue invalidation.
dma<n>_s_axis_c2h_cmpt_ctrl_user_trig I User can trigger the interrupt and the status descriptor write if they are enabled.
dma<n>_s_axis_c2h_cmpt_ctrl_cmpt_type[1:0] I

2’b00: NO_PLD_NO_WAIT. The CMPT packet does not have a corresponding payload packet, and it does not need to wait.

2’b01: NO_PLD_BUT_WAIT. The CMPT packet does not have a corresponding payload packet; however, it still needs to wait for the payload packet to be sent before sending the CMPT packet.

2’b10: RSVD.

2’b11: HAS_PLD. The CMPT packet has a corresponding payload packe, and it needs to wait for the payload packet to be sent before sending the CMPT packet.
dma<n>_s_axis_c2h_cmpt_ctrl_wait_pld_pkt_id[15:0] I The data payload packet ID that the CMPT packet needs to wait for before it can be sent.
dma<n>_s_axis_c2h_cmpt_ctrl_port_id[2:0] I Port ID.
dma<n>_s_axis_c2h_cmpt_ctrl_col_idx[2:0] I Color index that defines if the user wants to have the color bit in the CMPT packet and the bit location of the color bit if present.
dma<n>_s_axis_c2h_cmpt_ctrl_err_idx[2:0] I Error index that defines if the user wants to have the error bit in the CMPT packet and the bit location of the error bit if present.

dma<n>_s_axis_c2h_cmpt_ctrl_no_wrb_marker

I Disables CMPT packet during Marker transfer.

1'b0 : CMPT packets are sent to CMPT ring

1'b1 : CMPT packets are not sent to CMPT ring.

dma<n>_s_axis_c2h_cmpt_tvalid I Valid. dma<n>_s_axis_c2h_cmpt_tvalid must be asserted until dma<n>_s_axis_c2h_cmpt_tready is asserted.
dma<n>_s_axis_c2h_cmpt_tready O Ready.