AXI4-Stream C2H Interface - 3.4 English

Versal Adaptive SoC CPM DMA and Bridge Mode for PCI Express Product Guide (PG347)

Document ID
PG347
Release Date
2023-11-20
Version
3.4 English
Table 1. AXI4-Stream C2H Interface Descriptions
Port Name I/O Description
dma0_s_axis_c2h_tdata

[AXI_DATA_WIDTH-1:0]

I Supports 4 data widths: 64 bits, 128 bits, 256 bits, and 512 bits. Every C2H data packet has a corresponding C2H completion packet.
dma0_s_axis_c2h_dpar

[AXI_DATA_WIDTH/8-1 : 0]

I

Odd parity computed as bit per byte.

dma0_s_axis_c2h_ctrl_len [15:0] I Length of the packet. For 0 (zero) byte write, the length is 0. C2H stream packet data length is limited to 7 * descriptor size.
dma0_s_axis_c2h_ctrl_qid [10:0] I Queue ID.
dma0_s_axis_c2h_ctrl_imm_data I

Immediate data. This allows only the completion and no DMA on the data payload.

dma0_s_axis_c2h_ctrl_dis_cmpt I Disable completion
dma0_s_axis_c2h_ctrl_marker I Marker message used for making sure pipeline is completely flushed. After that, you can safely perform queue invalidation.
dma0_s_axis_c2h_ctrl_port_id [2:0] I Port ID.
dma0_s_axis_c2h_ctrl_user_trig I

User trigger. This can trigger the interrupt and the status descriptor write if they are enabled.

dma0_s_axis_c2h_mty [5:0] I Empty byte should be set in last beat.
dma0_s_axis_c2h_tvalid I Valid.
dma0_s_axis_c2h_tlast I Indicate last packet.
dma0_s_axis_c2h_tready O Ready.
dma0_s_axis_c2h_cmpt_data[127:0] I

Completion data from the user application. This contains information that is written to the completion ring in the host. This information includes the length of the packet transferred in bytes, error, color bit, and user data. Based on completion size, this could be 1 or 2 beats. Every C2H completion packet has a corresponding C2H data packet.

dma0_s_axis_c2h_cmpt_size[1:0] I

00: 8B completion.

01: 16B completion.

10: 32B completion.

11: unknown.

dma0_s_axis_c2h_dmpt_dpar[3:0] I

Odd parity computed as bit per word.

dma0_s_axis_c2h_cmpt_dpar[0] is parity over dma0_s_axis_c2h_cmpt_data[31:0].

dma0_s_axis_c2h_cmpt_dpar[1] is parity over dma0_s_axis_c2h_cmpt_data[63:31], and so on.

dma0_s_axis_c2h_cmpt_tvalid I Valid
dma0_s_axis_c2h_cmpt_tlast I Indicates the end of the completion data transfer.
dma0_s_axis_c2h_cmpt_tready O Ready