AXI4-Stream C2H Ports - 3.3 English

Versal ACAP CPM DMA and Bridge Mode for PCI Express Product Guide (PG347)

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Table 1. AXI4-Stream C2H Port Descriptions
Port Name I/O Description


I It supports 4 data widths: 64 bits, 128 bits, 256 bits, and 512 bits. Every C2H data packet has a corresponding C2H completion packet



32 bit CRC value for that beat

IEEE 802.3 CRC-32 Polynomial

IP samples CRC value only when s_axis_c2h_tlast is asserted

dma<n>_s_axis_c2h_ctrl_len [15:0] I Length of the packet. For ZERO byte write, the length is 0.

C2H stream packet data length is limited to 31 * c2h buffer size

ctrl_len is in bytes and should be valid in first beat of the packet

dma<n>_s_axis_c2h_ctrl_qid [11:0] I Queue ID
dma<n>_s_axis_c2h_ctrl_has_cmpt I 1'b1: The data packet has a completion;

1'b0: The data packet doesn't have a completion

dma<n>_s_axis_c2h_ctrl_marker I Marker message used for making sure pipeline is completely flushed. After that, you can safely do queue invalidation
dma<n>_s_axis_c2h_ctrl_port_id [2:0] I Port ID
dma<n>_s_axis_c2h_ecc[6:0] I Output of the Xilinx® Error Correction Code (ECC) core. ECC IP input is described below
dma<n>_s_axis_c2h_mty [5:0] I Empty byte should be set in last beat
dma<n>_s_axis_c2h_tvalid I Valid
dma<n>_s_axis_c2h_tlast I Indicate last packet
dma<n>_s_axis_c2h_tready O Ready

To generate ECC signals for C2H control bus dma<n>_s_axis_c2h_ctrl_ecc[6:0], use Xilinx Error

Correction Code (ECC) IP. Input signals to ECC IP are listed below and you have to maintain the order that is listed below.

Input to ECC IP using ecc_data_in[56:0]

assign ecc_data_in[56:0] = { 24'h0, //reserved
                    dma<n>_s_axis_c2h_ctrl_has_cmpt, //has compt
                    dma<n>_s_axis_c2h_ctrl_marker, //marker
                    dma<n>_s_axis_c2h_ctrl_port_id, //port_id
                    dma<n>_s_axis_c2h_ctrl_qid, // Qid 
                    dma<n>_s_axis_c2h_ctrl_len}; //length