Simulation models for the AXI-MM and AXI-ST options can be generated and simulated. The simple simulation model options enable you to develop complex designs.
AXI-MM Mode
The example design for the AXI4 Memory Mapped (AXI-MM) mode has 512 KB block RAM on the user side, where the data can be written to the block RAM, and read from block RAM to the host.
After the host to Card (H2C) transfer is started, the DMA reads data from the host memory, and writes to the block RAM. After the transfer is completed, the DMA updates the write back status and generates an interrupt (if enabled). Then, the card to host (C2H) transfer is started, and the DMA reads data from the block RAM and writes to the host memory. The original data is compared with the C2H write data. H2C and C2H are set up with one descriptor each, and the total transfer size is 128 bytes.
AXI-ST Mode
The example design for the AXI4-Stream (AXI-ST) mode has a data check that checks the data from the H2C transfer, and has a data generator that generates the data for C2H transfer.
After the H2C transfer is started, the DMA engine reads data from the host memory, and writes to the user side. After the transfer is completed, the DMA updates write back status and generates an interrupt (if enabled). The data checker on the user side checks for a predefined data to be present, and the result is posted in a predefined address for the user application to read.
After the C2H transfer is started, the data generator generates predefined data and associated control signals, and sends them to the DMA. The DMA transfers data to the Host, updates the completion (CMPT) ring entry/status, and generates an interrupt (if enabled).
H2C and C2H are set up with 16 descriptor each, and the total transfer size is 128 bytes.