C2H Completion Context Structure - 3.3 English

Versal ACAP CPM DMA and Bridge Mode for PCI Express Product Guide (PG347)

Document ID
PG347
Release Date
2022-11-02
Version
3.3 English

The completion context is used by the completion engine.

Table 1. C2H Completion Context Structure Defintion
Bit Bit Width Field Name Description
[127:126] 2 rsvd Reserved
[125] 1 full_upd Full Update

If reset, then the Completion-CIDX-update is allowed to update only the CIDX in this context.

If set, then the Completion CIDX update can update the following fields in this context:

timer_ix

counter_ix

trig_mode

en_int

en_stat_desc

[124] 1 timer_running If set, it indicates that a timer is running on this queue. This timer is for the purpose of C2H interrupt moderation. Ideally, the software must ensure that there is no running timer on this QID before shutting the queue down. This is a field used internally by HW. The SW must initialize it to 0 and then treat it as read-only.
[123] 1 user_trig_pend If set, it indicates that a user logic initiated interrupt is pending to be generated. The user logic can request an interrupt through the s_axis_c2h_ctrl_user_trig signal. This bit is set when the user logic requests an interrupt while another one is already pending on this QID. When the next Completion CIDX update is received by QDMA, this pending bit may or may not generate an interrupt depending on whether or not there are entries in the Completion ring waiting to be read. This is a field used internally by HW. The SW must initialize it to 0 and then treat it as read-only.
[122:121] 2 err Indicates that the C2H Completion Context is in error. This is a field written by HW. The SW must initialize it to 0 and then treat it as read-only. The following errors are indicated here:

0: No error.

1: A bad CIDX update from software was detected.

2: A descriptor error was detected.

3: A Completion packet was sent by the user logic when the Completion Ring was already full.

[120] 1 valid Context is valid.
[119:104] 16 cidx Current value of the hardware copy of the Completion Ring Consumer Index.
[103:88] 16 pidx Completion Ring Producer Index. This is a field written by HW. The SW must initialize it to 0 and then treat it as read-only.
[87:86] 2 desc_size Completion Entry Size:

0: 8B

1: 16B

2: 32B

3: Unknown

[85:28] 58 baddr_64 Base address of Completion ring – bit [63:6].
[27:24] 4 qsize_idx Completion ring size index to ring size registers.
[23] 1 color Color bit to be used on Completion.
[22:21] 2 int_st Interrupt State:

0: ISR

1: TRIG

This is a field used internally by HW. The SW must initialize it to 0 and then treat it as read-only.

Because it is out of reset, the HW initializes into ISR state, it is not sensitive to trigger events. If SW desires interrupts or status writes, it must send an initial Completion CIDX update. This makes the HW move into TRIG state and as a result it becomes sensitive to any trigger conditions.

[20:17] 4 timer_idx Index to timer register for TIMER based trigger modes.
[16:13] 4 counter_idx Index to counter register for COUNT based trigger modes.
[12:5] 8 fnc_id Function ID
[4:2] 3 trig_mode

Interrupt and Completion Status Write Trigger Mode:

0x0: Disabled

0x1: Every

0x2: User_Count

0x3: User

0x4: User_Timer

0x5: User_Timer_Count

[1] 1 en_int Enable Completion interrupts.
[0] 1 en_stat_desc Enable Completion Status writes.