QDMA and AXI Bridge runs on clock that is provide by user. This is a change
from CPM4 (where the clock is provided by the IP). You must provide a clock
dma<n>_intrfc_clk, which will be used by the IP.
All the input ports and output ports will be driven or loaded using this clock.
Because this is an independent clock provided by the user there are some
restrictions on clock frequency based on the IP configurations, which are listed
|Gen4x16||433 MHz 1|
|Gen5x8||433 MHz 1|
The input clock frequency (
cpm_pl_axi<n>_clk for Gen3x16 and Gen4x8 configurations is
250 Mhz. For Gen4x16 and Gen5x8 configurations, the maximum input clock frequency
allowed is 433 Mhz for a -3HP device. For other device speed grades, refer to the
corresponding device data sheet to know the maximum frequency applicable to those
For QDMA1 AXI-MM interface there are two more clock inputs that you
must provide clocks,
PCIe Ref Clock
Each link partner device shares the same reference clock source. The following figures show a system using a 100 MHz reference clock. Even if the device is part of an embedded system, if the system uses commercial PCI Express® root complexes or switches along with typical motherboard clocking schemes, synchronous clocking should be used.