At this point, the FPGA design has been loaded, the PCIe link has been
established, the HSDP-PCIe driver has been compiled and installed with the correct
configuration values, and the
hw_server application has
been started on the debug Host PC. The remaining step is to connect to
hw_server and begin connecting to the debug cores to
exchange and display debug data.
- Launch Vivado.
- Select Open Hardware Manager from the Flow Navigator.
- In the Hardware Manager, select .
- Connect to the
hw_serverapplication from the Vivado IDE.
- If the debug host is remote, in the Hardware Server Settings window, modify the host name field to the remote server that is running hw_server and the port number field, if using the non-default port.
- If the debug host is local, in the Hardware Server Settings window, select the Local Server option for the Connect to: field.
- If successful, a hardware target should be populated for selection,
then click through to Finish.
- The target device should be in the Hardware window and a probes file
can now be specified in the Hardware Device Properties window after opening the
hardware target and the debug core data is displayedNote: If using mgmt mode for debug, the hard block debug cores are accessible for debug, while only user debug cores are present when using user mode for debug.
- If using mgmt mode for debug, a user can connect to the debug host
PC through the XSDB application and issue direct AXI reads and writes through the