Deliver Programming Images to Silicon - 3.3 English

Versal ACAP CPM DMA and Bridge Mode for PCI Express Product Guide (PG347)

Document ID
PG347
Release Date
2022-11-02
Version
3.3 English

The purpose of Tandem Configuration is to be able to program the PCIe endpoint(s) within 120 ms before link training starts. The stage 1 file configures the CPM, GTs, and NoC connection required for stage 1 operation. These blocks then become active and can interact with the host to perform PCIe enumeration.

When using Tandem PROM, configuration of the remainder of the device continues to load from the same programming image on the same primary boot device while the PCIe endpoint(s) are up and running. There are no requirements for PERSIST or similar restrictions as was the case with UltraScale+ and prior FPGA architectures.

When using Tandem PCIe, the remainder of the device programming is done by delivering the stage 2 .pdi from the PCIe host as a secondary boot device. There are four data paths in the CPM through which the tandem2.pdi file can be loaded from PCIe into the PMC Slave Boot Interface. The specific path you select is determined based on the IP configuration desired for your specific application. These are enumerated below.

QDMA MM Data Path
If the QDMA Memory Mapped data path is enabled, it can be used to download through PCIe into the FPGA Slave Boot Interface at a maximum rate of 3.2 Gbytes/s. This is limited by the programming rate of the Slave Boot Interface. Xilinx provides sample QDMA drivers and software (see Note below). This data path can only be used with PCIe controller 0 because CPM controller 1 does not support hardened QDMA operation.
XDMA MM Data Path
If the XDMA Memory Mapped data path is enabled, it can be used to download through PCIe into the FPGA Slave Boot Interface at a maximum rate of 3.2 Gbytes/s. This is limited by the programming rate of the FPGA Slave Boot Interface. Xilinx provides sample XDMA drivers and software (see Note below). This data path can only be enabled with PCIe controller 0 because CPM controller 1 does not support hardened XDMA operation.
AXI Master Bridge
If the AXI Master bridge data path is enabled, it can be used to download through PCIe into the FPGA Slave Boot Interface at a maximum rate limited by the host’s ability to generate PCIe transactions (typically around 700 Mbytes/s for 64-byte transfers from the host). Xilinx does not provide sample drivers and software for this because either the XDMA or QDMA data paths are typically enabled with this mode and allow for higher transfer rates. This data path can only be enabled with PCIe controller 0 because CPM controller 1 does not support hardened AXI Master Bridge operation.
Versal MCAP VSEC
Both controllers in CPM can enable the MCAP Vendor Specific Extended Capability. This capability functions differently from UltraScale and UltraScale+ solutions. It can be used to download through PCIe into the FPGA Slave Boot Interface at a maximum rate limited by the host’s ability to generate 32-bit PCIe configuration transactions (typically lower than 1 Mbytes/s). This mode of configuration should only be used when the other three data paths are not available. This includes PCIe Streaming and CCIX modes on either controller. For more information, see Versal ACAP CPM Mode for PCI Express Product Guide (PG346).
Note: Xilinx provides sample drivers and software to enable stage 2 programming. These drivers can be found at https://github.com/Xilinx/dma_ip_drivers.