Error Interrupt - 3.3 English

Versal ACAP CPM DMA and Bridge Mode for PCI Express Product Guide (PG347)

Document ID
Release Date
3.3 English

There are Leaf Error Aggregators in different places. They log the errors and propagate the errors to the Central Error Aggregator. Each Leaf Error Aggregator has an error status register and an error mask register. The error mask is enable mask. Irrespective of the enable mask value, the error status register always logs the errors. Only when the error mask is enabled, the Leaf Error Aggregator will propagate the error to the Central Error Aggregator.

The Central Error Aggregator aggregates all of the errors together. When any error occurs, it can generate an Error Interrupt if the err_int_arm bit is set in the error interrupt register QDMA_GLBL_ERR_INT (0B04). The err_int_arm bit is set by the software and cleared by the hardware when the Error Interrupt is taken by the Interrupt Engine. The Error Interrupt is for all of the errors including the H2C errors and C2H errors. The Software must set this err_int_arm bit to generate interrupt again.

The Error Interrupt supports the direct interrupt only. Register QDMA_GLBL_ERR_INT bit[23], en_coal must always be programmed to 0 (direct interrupt).

The Error Interrupt gets the vector from the error interrupt register QDMA_GLBL_ERR_INT. For the direct interrupt, the vector is the interrupt vector index of the MSI-X table.

Here are the processes of the Error Interrupt.

  1. Reads the Error Interrupt register QDMA_C2H_GLBL_INT (0B04) to get function and vector numbers.
  2. Sends out the PCIe MSI-X message.

The following figure shows the error interrupt register block diagram.

Figure 1. Error Interrupt Handling