This example shows the generic settings to set up three independent AXI BARs and address translation of AXI addresses to a remote 32-bit address space for PCIe. This setting of AXI BARs does not depend on the BARs for PCIe in the AXI Bridge functional mode.
In this example, where C_AXIBAR_NUM=3, the following assignments for each range are made:
AXI_ADDR_WIDTH=48
C_AXIBAR_0=0x00000000_12340000
C_AXI_HIGHADDR_0=0x00000000_1234FFFF (64 Kbytes)
C_AXIBAR2PCIEBAR_0=0x00000000_56710000 (Bits 63-32 are zero in order to produce a
32-bit PCIe TLP. Bits 15-0 must be zero based on the AXI BAR aperture size. Non-zero
values in the lower 16 bits are invalid translation values.)
C_AXIBAR_1=0x00000000_ABCDE000
C_AXI_HIGHADDR_1=0x00000000_ABCDFFFF (8 Kbytes)
C_AXIBAR2PCIEBAR_1=0x00000000_FEDC0000 (Bits 63-32 are zero in order to produce a
32-bit PCIe TLP. Bits 12-0 must be zero based on the AXI BAR aperture size. Non-zero
values in the lower 13 bits are invalid translation values.)
C_AXIBAR_2=0x00000000_FE000000
C_AXI_HIGHADDR_2=0x00000000_FFFFFFFF (32 Mbytes)
C_AXIBAR2PCIEBAR_2=0x00000000_40000000 (Bits 63-32 are zero in order to produce a
32-bit PCIe TLP. Bits 24-0 must be zero based on the AXI BAR aperture size. Non-zero
values in the lower 25 bits are invalid translation values.)
Figure 1. Example 1 Settings

- Accessing the Bridge
AXIBAR_0
with address0x0000_12340ABC
on the AXI bus yields0x56710ABC
on the bus for PCIe.
Figure 2. AXI to PCIe Address Translation

- Accessing the Bridge AXIBAR_1 with address
0x0000_ABCDF123
on the AXI bus yields0xFEDC1123
on the bus for PCIe. - Accessing the Bridge AXIBAR_2 with address
0x0000_FFEDCBA
on the AXI bus yields0x41FEDCBA
on the bus for PCIe.