Function Status Register (0x1000) - 3.3 English

Versal ACAP CPM DMA and Bridge Mode for PCI Express Product Guide (PG347)

Document ID
PG347
Release Date
2022-11-02
Version
3.3 English
Table 1. Function Status Register (0x1000)
Bit Index Default Access Type Field Description
[31:12] 0 NA Reserved Reserved
[11:4] 0 RO cur_src_fn This field is for PF use only.

The source function number of the message on the top of the incoming request queue.

[2] 0 RO ack_status This field is for PF use only.

The status bit will be set when any bit in the acknowledgement status register is asserted.

[1] 0 RO o_msg_status For VF: The status bit will be set when VF driver write msg_send to its command register. When the associated PF driver sends acknowledgement to this VF, the hardware clears this field. The VF driver is not allow to update any content in its outgoing mailbox memory (OMM) while o_msg_status is asserted. Any illegal writes to the OMM are discarded (optionally, this can cause an error in the AXI4-Lite response channel).

For PF: The field indicated the message status of the target FN which is specified in the Target FN Register. The status bit is set when PF driver sends the msg_send command. When the corresponding function driver sends acknowledgement through msg_rcv, the hardware clears this field. The PF driver is not allow to update any content in its outgoing mailbox memory (OMM) while o_msg_status(target_fn_id) is asserted. Any illegal writes to the OMM are discarded (optionally, this can cause an error in the AXI4-Lite response channel).

[0] 0 RO i_msg_status For VF: When asserted, a message in the VF's incoming Mailbox memory is pending for process. The field is cleared after the VF driver writes msg_rcv to its command register.

For PF: When asserted, the messages in the incoming Mailbox memory are pending for process. The field is cleared only when the event queue is empty.