GT Selection and Pin Planning for CPM4 - 3.3 English

Versal ACAP CPM DMA and Bridge Mode for PCI Express Product Guide (PG347)

Document ID
PG347
Release Date
2022-11-02
Version
3.3 English

This appendix provides guidance on gigabit transceiver (GT) selection for applicable Versal® devices and some key recommendations that should be considered when selecting the GT locations. This appendix provides guidance for CPM, PL PCIe® and PHY IP based solutions. In this guide, the CPM related guidance is of primary importance, while the other related guidance might be relevant and is provided for informational purposes.

A GT Quad is comprised of four GT lanes. GT Quad and ref clock locations for CPM4 are in fixed locations depending on the desired link configuration (see GT Quad Locations). When selecting GT Quads for the PHY IP based solution with Xilinx PCIe MAC, Xilinx recommends that you use the GT Quads most adjacent to the Xilinx PCIe macro. While this is not required, it improves place, route, and timing for the design.

  • Link widths of x1, x2, and x4 require one bonded GT Quad and should not split lanes between two GT Quads.
  • A link width of x8 requires two adjacent GT Quads that are bonded and are in the same SLR.
  • A link width of x16 requires four adjacent GT Quads that are bonded and are in the same SLR.
  • PL PCIe blocks should use GTs adjacent to the PCIe block where possible.
  • CPM has a fixed connectivity to GTs based on the CPM configuration.

For GTs on the left side of the device, PCIe lane 0 is placed in the bottom-most GT of the bottom-most GT Quad. Subsequent lanes use the next available GTs moving vertically up the device as the lane number increments. This means that the highest PCIe lane number uses the top-most GT in the top-most GT Quad that is used for PCIe.

For GTs on the right side of the device, PCIe lane 0 is placed in the top-most GT of the top-most GT Quad. Subsequent lanes use the next available GTs moving vertically down the device as the lane number increments. This means that the highest PCIe lane number uses the bottom-most GT in the bottom-most GT Quad that is used for PCIe.

The PCIe reference clock uses GTREFCLK0 in the PCIe lane 0 GT Quad for x1, x2, x4, and x8 configurations. For x16 configurations the PCIe reference clock should use GTREFCLK0 on a GT Quad associated with lanes 8-11. This allows the clock to be forwarded to all 16 PCIe lanes.

The PCIe reset pins for CPM designs must connect to one of specified pins for each of the two PCIe controllers. The PCIe reset pin for PL PCIe and PHY IP designs can be connected to any compatible PL pin location, or the CPM PCIe reset pins when the corresponding CPM PCIe controller is not in use. This is summarized in the following table:

Table 1. PCIe Controller Reset Pin Locations
Versal PCIe Controller Versal Reset Pin Location
CPM PCIe Controller 0 PS MIO 18
PMC MIO 24
PMC MIO 38
CPM PCIe Controller 1 PS MIO 19
PMC MIO 25
PMC MIO 39
PL PCIe Controllers Any compatible single-ended PL I/O pin.
Versal ACAP PHY IP Any compatible single-ended PL I/O pin.

PCIe PHY IP has two Vivado Tcl parameters. lane_reversal with values true or false (Default). lane_order which is only applicable to x1 and x2 configurations with values bottom (Default) or Top. For example in a x2 design, by default PIPE signals of the PCIe MAC[1:0] connects to PIPE signals of the GT QUAD[1:0]. When we apply lane_reversal {true} then PIPE signals of the PCIe MAC[1:0] connects to PIPE signals of the GT QUAD[0:1]. When we apply lane_order {Top} then PIPE signals of the PCIe MAC[1:0] connects to PIPE signals of the GT QUAD[3:2].