GT Selection and Pin Planning for CPM5 - 3.3 English

Versal ACAP CPM DMA and Bridge Mode for PCI Express Product Guide (PG347)

Document ID
PG347
Release Date
2022-11-02
Version
3.3 English
CAUTION:
The guidance provided in this appendix contains preliminary information and is subject to change without notice.

This appendix provides guidance on gigabit transceiver (GTYP) selection for CPM5 and key recommendations to be considered during pin planning. For each PCIe interface, these include:

  • GTYP quad placement
  • REFCLK placement
  • RESET placement

CPM5 has dedicated connectivity to a specific set of four GTYP quads which are adjacent to each other, and adjacent to CPM5. If unused by CPM5, certain quads may be available for use with the high-speed debug port (HSDP), but no quad can be bypassed to the programmable logic. The remaining GT in the device are available for other use cases, if the GT of interest provide the necessary protocol support as required for the desired use cases.

Through the GTYP quads with dedicated connectivity to the CPM5, specific REFCLK inputs must be used to provide a reference clock to GTYP quads, which internally provide derived clocks to the CPM5. In the common case of add-in-card designs, the reference clock is sourced from the edge connector. In other cases, such as system-board designs, embedded designs, and cabled interconnect, a local oscillator is typically required.

As part of the VersalĀ® architecture integrated shell, specific reset inputs must be used to provide a reset to the GTYP and the CPM5. In the common case of add-in-card designs, the reset is sourced from the edge connector. In the case of a system-board or embedded design, the system is responsible for generating reset signals and sourcing them to devices as required for the desired use case. Where cabled interconnect is used, consult the cable specification for information about if, and how, it accommodates sideband signaling for reset.

The remainder of this appendix is divided into these sections:
  1. General Guidance for CPM5
    • Most designers working with CPM5 devices will require the guidance in this section.
  2. Guidance for CPM5 in Specifically Identified Engineering Sample Devices
    • Designers working with CPM5 in specifically identified engineering sample devices will require the guidance in this section.
  3. Guidance for CPM5 Migration from Specifically Identified Engineering Sample Devices
    • Designers intending to migrate their design containing CPM5 from specifically identified engineering sample devices into other devices will require the guidance in all sections.