GTYP Quad and REFCLK Considerations - 3.3 English

Versal ACAP CPM DMA and Bridge Mode for PCI Express Product Guide (PG347)

Document ID
PG347
Release Date
2022-11-02
Version
3.3 English

In migration, the lane ordering for each controller configured for x16 or x8 link widths will reverse within the GTYP quads accessible to each controller. For these designs, the lane reversal will be transparent under the assumption lane reversal by the IP is used. REFCLK placements for x16 or x8 link widths do not change.

For designs using x4 or narrower link widths, the lane ordering will be unchanged during migration. REFCLK placements also do not change.

Consult the provided placement tables. For additional migration support, contact your Xilinx representative.