GTYP Quad and REFCLK Placements - 3.3 English

Versal ACAP CPM DMA and Bridge Mode for PCI Express Product Guide (PG347)

Document ID
PG347
Release Date
2022-11-02
Version
3.3 English

Allowed placements are shown in the table below. Placements are determined by CIPS IP configuration GUI as part of CPM configuration selections.

Table 1. Allowable GTYP Quad Placements
Board CPM5 PCIE Controller Width Configuration GTYP Transceiver Quad (Package Bank) Channels CPM5 PCIE Controller GTYP Reference Clock Other Supported Width Configurations Lane Reversal
1 0 Quad 3 (Bank 105) Quad 2 (Bank 104) Quad 1 (Bank 103) Quad 0 (Bank 102)
3 2 1 0 3 2 1 0 3 2 1 0 3 2 1 0 1 0
x16 -- x16 Controller 0 [15:0] -- Quad 104, Refclk 0 -- By IP
x8, x8 x8 x8 Controller 1 [7:0] Controller 0 [7:0] Quad 104, Refclk 0

Quad 105, Refclk 0 1

Quad 102, Rekclk 0

Quad 103, Refclk 0 1

-- By IP
x8 x8 -- Controller 1 [7:0] -- Quad 104, Refclk 0

Quad 105, Refclk 0 1

-- -- By IP
x8 -- x8 -- Controller 0 [7:0] -- Quad 102, Refclk 0

Quad 103, Refclk 0 1

-- By IP
x4, x4 x4 x4 -- Controller 1 [3:0] -- Controller 0 [3:0] Quad 104, Refclk 0 Quad 102, Refclk 0 -- On PCB
x4 x4 -- -- Controller 1 [3:0] -- Quad 104, Refclk 0 -- -- On PCB
x4 -- x4 -- -- Controller 0 [3:0] -- Quad 102, Refclk 0 -- On PCB
x4, x8 x4 x8 -- Controller 1 [3:0] Controller 0 [7:0] Quad 104, Refclk 0 Quad 102, Refclk 0

Quad 103, Refclk 0 1

-- x4 on PCB

x8 by IP

x8, x4 x8 x4 Controller 1 [7:0] -- Controller 0 [3:0] Quad 104, Refclk 0

Quad 105, Refclk 0 1

Quad 102, Refclk 0 -- x8 by IP

x4 on PCB

  1. Not required for 16 GT/sec/lane data rate or lower.

Board designs for x2 and x1 must use x4 guidance. For x2 board designs, based on the controller to be used, connect to controller lane numbers Controller 0 [1:0] or Controller 1 [1:0]. Similarly, for x1 board designs, connect to controller lane numbers Controller 0 [0] or Controller 1 [0]. Note that controller lane numbers might not be the same as physical GTYP channel numbers in a quad. Consult the provided placement table.