H2C Stream Status Descriptor Writeback - 3.3 English

Versal ACAP CPM DMA and Bridge Mode for PCI Express Product Guide (PG347)

Document ID
PG347
Release Date
2022-11-02
Version
3.3 English

When feeding the descriptor information on the bypass input interface, the user logic can request the QDMA to send a status write back to the host when it is done fetching the data from the host. The user logic can also request that a status be issued to it when the DMA is done. These behaviors can be controlled using the sdi and mrkr_req inputs in the bypass input interface.

The H2C writeback status register is located after the last entry of the H2C descriptor list.

Note: The format of the H2C-ST status descriptor written to the descriptor ring is different from that written into the interrupt coalesce entry.
Table 1. AXI4-Stream H2C Writeback Status Descriptor Structure
Bit Bit Width Field Name Description
[63:32] 32 reserved Reserved
[47:32] 16 pidx Producer Index
[31:16] 16 cidx Consumer Index
[15:2] 14 reserved Reserved (Producer Index)
[1:0] 2 error Error

0x0 : No Error

0x1 : Descriptor or data error was encountered on this queue

0x2 and 0x3 : Reserved