HSDP-over-PCIe Enabled FPGA Design - 3.3 English

Versal ACAP CPM DMA and Bridge Mode for PCI Express Product Guide (PG347)

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3.3 English

Traditionally, hardware debug through Vivado is performed over a JTAG interface. For Versal ACAP, the JTAG datapath to the DPC is hardened and abstracted away using Vivado IDE. Making debug seamless requires that the connections are established among the debug target(s), DPC, and debug target clock(s) are active and reset(s) are deasserted. To enable the HSDP-over-PCIe feature on a Versal ACAP device, there are several design requirements that must be met. As mentioned previously, there are two distinct methods to exercise the HSDP-over-PCIe feature such as mgmt mode and user mode. Each of these methods has its own design requirements and supporting driver code.