Hardware Descriptor Context Structure (0x2 C2H and 0x3 H2C) - 3.3 English

Versal ACAP CPM DMA and Bridge Mode for PCI Express Product Guide (PG347)

Document ID
PG347
Release Date
2022-11-02
Version
3.3 English
Table 1. Hardware Descriptor Structure Definition
Bit Bit Width Field Name Description
[47] 1 reserved Reserved
[46:43] 4 fetch_pnd Descriptor fetch pending
[42] 1 evt_pnd Event pending
[41] 1 idl_stp_b

Queue invalid and no descriptors pending.

This bit is set when the queue is enabled. The bit is cleared when the queue has been disabled (software context qen bit) and no more descriptors are pending.

[0] Queue is disabled (software context qen bit) and no more descriptors pending.

[1] Queue is enabled.

[40] 1 dsc_pnd Descriptors pending. Descriptors are defined to be pending if the last CIDX completed does not match the current PIDX.
[39:32] 8   Reserved
[31:16] 16 crd_use Credits consumed. Applicable if fetch credits are enabled in the software context.
[15:0] 16 cidx Consumer index of last fetched descriptor.