IP Connections - 3.3 English

Versal ACAP CPM DMA and Bridge Mode for PCI Express Product Guide (PG347)

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3.3 English
Next, add signal connections between the IP in the Vivado IP integrator.
  1. Make the connections between the IP cores as shown in following figure.
  2. Set GT_REFCLK_D, GT_PCIEA0_RX, GT_PCIEA0_TX, SYS_CLK0_IN and CH0_DDR4_0 as primary ports. To do so:
    1. Select pins GT_REFCLK_D, GT_PCIEA0_RXand GT_PCIEA0_TX of versal_cips_0, SYS_CLK0_IN of clk_gen_sim_0, and CH0_DDR4_0 of axi_noc_0 by pressing Ctrl+click.
    2. Click the Make External (Ctrl + T) icon in the toolbar at the top of the canvas.