Interrupt Aggregation Entry - 3.3 English

Versal ACAP CPM DMA and Bridge Mode for PCI Express Product Guide (PG347)

Document ID
PG347
Release Date
2022-11-02
Version
3.3 English

This is the Interrupt Aggregation Ring entry structure. It has 8B data.

Table 1. Interrupt Aggregation Ring Entry Structure
Signal Bit Owner Description
Coal_color [63] DMA The color bit of the Interrupt Aggregation Ring. This bit inverts every time pidx wraps around on the Interrupt Aggregation Ring.
Qid [62:39] DMA This is from Interrupt source. Queue ID.
Int_type [38:38] DMA 0: H2C

1: C2H

Rsvd [37:37] DMA Reserved
Stat_desc [36:0] DMA This is the status descriptor of the Interrupt source.

The following is the information in the stat_desc.

Table 2. stat_desc Information
Signal Bit Owner Description
Error [36:35] DMA

This is from interrupt source: c2h_err[1:0], or h2c_err[1:0].

Int_st [34:33] DMA This is from Interrupt source. Interrupt state.

0: WRB_INT_ISR

1: WRB_INT_TRIG

2: WRB_INT_ARMED

Color [32:32] DMA This is from Interrupt source. This bit inverts every time pidx wraps around and this field gets copied to color field of descriptor.
Cidx [31:16] DMA This is from Interrupt source. Cumulative consumed pointer.
Pidx [15:0] DMA This is from Interrupt source. Cumulative pointer of total interrupt Aggregation Ring entry written.