The following is the Interrupt Context Structure (0x8).
|rsvd||[255:126]||Driver||Reserved. Initialize to 0s|
|rsvd||[113:83]||Driver||Reserved. Initialize to 0s|
|at||||Driver||1'b0: un-translated address
1'b1: translated address
|pidx||[81:70]||DMA||Producer Index, updated by DMA IP.|
Interrupt Aggregation Ring size:
0: 4 KB
1: 8 KB
2: 12 KB
3: 16 KB
4: 20 KB
5: 24 KB
6: 28 KB
7: 32 KB
|baddr_4k||[66:15]||Drive||Base address of Interrupt Aggregation Ring – bit [63:12]|
|vec||[11:1]||Driver||Interrupt vector index in msix table|
The software needs to size the Interrupt Aggregation Ring appropriately. Each source can send up to three messages to the ring. Therefore, the size of the ring needs satisfy the following formula.
Number of entry ≥ 3 x number of queues
The Interrupt Context is programmed by the context access. The QDMA_IND_CTXT_CMD.Qid has the ring index, which is from the interrupt source. The operation of MDMA_CTXT_CMD_CLR can clear all of the bits in the Interrupt Context. The MDMA_CTXT_CMD_INV can clear the valid bit.
- Context access through QDMA_TRQ_SEL_IND:
- QDMA_IND_CTXT_CMD.Qid = Ring index
- QDMA_IND_CTXT_CMD.Sel = MDMA_CTXT_SEL_INT_COAL (0x8)
- QDMA_IND_CTXT_CMD.cmd.Op =
After the interrupt engine looks up the Interrupt Context, the interrupt engine writes to the Interrupt Aggregation Ring. The interrupt engine also updates the Interrupt Context with the new PIDX, color, and the interrupt state.