Introduction to the CPM5 - 3.3 English

Versal ACAP CPM DMA and Bridge Mode for PCI Express Product Guide (PG347)

Document ID
PG347
Release Date
2022-11-02
Version
3.3 English

The integrated block for PCIe® Rev. 5.0 with DMA and CCIX Rev. 1.0 (CPM5) is shown in the following figure.

Figure 1. CPM5 Sub-Block for PCIe Function (CPM5 PCIE)

CPM Components

The CPM includes multiple IP cores:
Controllers for PCIe
The CPM contains two instances of the Xilinx controller for PCIe: PCIE Controller 0 and PCIE Controller 1. Both controllers can have CCIX capabilities and also both controllers are capable of acting as an AXI bridge and as a DMA master. The controllers interface with the GTs through the XPIPE interface.
Coherent Mesh Network
The CPM has a Coherent Mesh Network (CMN) (not shown) that forms the cache coherent interconnect block in the CPM that is based on the Arm® CMN600 IP. There are two instances of L2 cache and CHI PL Interface (CPI) blocks in the CPM (also not shown).
DMA / AXI Bridge
CPM Controller 0 and Controller 1 both have hardened DMA/AXI Bridge. The CPM has Queue DMA Subsystem for PCIe (QDMA) for data transfer using Direct Memory Access (DMA). The DMA cores are used for data transfer between the programmable logic (PL) to the host, and from the host to PL. The DMA cores can also transfer data between the host and the network on chip (NoC) which provides a high bandwidth to other NoC ports including the available DDR memory controllers (DDRMC). The CPM has an AXI Bridge Subsystem for PCIe (AXI Bridge) IP for AXI-to-host communication.
Important: XDMA is not supported for CPM5.

The CPM includes a clock/reset block that houses phase-locked loop (PLL) and clock dividers. The CPM also includes the system-on-a-chip (SoC) debug component for transaction-level debug. Several APB and AXI interfaces are used between blocks in the CPM for configuration.

DMA Data Transfers

DMA data transfers can be initiated from both Controller 0 and from Controller 1. There are some limitations based on which DMA controller is used.

  • PCIE Controller 0
    • Data transfer width can be x16, x8, x4, x2 or x1
    • AXI4 MM data can only be transferred through NoC. From NoC data can be steered to DDR or to the programmable logic.
  • PCIE Controller 1
    • Data transfer width can be x8, x4, x2 or x1 (Not x16)
    • AXI4 MM data can be transferred through NoC or directly to PL logic. This is possible by setting Host profile programming. See Host Profile.

DMA transfers can be categorized into two different datapaths.

Data path from CPM to NoC to PL
All AXI Memory Mapped signals are connected from the DMA to the AXI interconnect. These signals are then routed to the Non-Coherent interconnect in the CPM block. They then connect to the PS interconnect and the NoC. From the NoC, the signal can be directed to any block (DDR or block RAM) based on the user design. The figure below shows the datapath to NoC in red.

Controller 1 QDMA can transfer AXI4 Memory Mapped signals directly to the PL or to the NoC and then to PL based on host profile programming.

Data path from CPM directly to PL
All AXI4-Stream signals and other side band signals, like clock and reset, are routed directly to the PL. The figure below shows the data path to the PL in green.
Figure 2. Controller 0 QDMA Data Paths
Figure 3. Controller 1 QDMA Data Paths